Document
74AXP1G58
Low-power configurable multiple function gate
Rev. 4 — 7 October 2021
Product data sheet
1. General description
The 74AXP1G58 is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions AND, OR, NAND, NOR, XOR, inverter and buffer. All inputs can be connected directly to VCC or GND.
This device ensures very low static and dynamic power consumption across the entire VCC range from 0.7 V to 2.75 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
2. Features and benefits
• Wide supply voltage range from 0.7 V to 2.75 V • Low input capacitance; CI = 0.5 pF (typical) • Low output capacitance; CO = 1.0 pF (typical) • Low dynamic power consumption; CPD = 2.7 pF at VCC = 1.2 V (typical) • Low static power consumption; ICC = 0.6 μA (85 °C maximum) • High noise immunity • Complies with JEDEC standard:
• JESD8-12A.01 (1.1 V to 1.3 V) • JESD8-11A.01 (1.4 V to 1.6 V) • JESD8-7A (1.65 V to 1.95 V) • JESD8-5A.01 (2.3 V to 2.7 V) • ESD protection: • HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV • CDM JESD22-C101E exceeds 1000 V • Latch-up performance exceeds 100 mA per JESD 78 Class II • Inputs accept voltages up to 2.75 V • Low noise overshoot and undershoot < 10% of VCC • IOFF circuitry provides partial power-down mode operation • Multiple package options • Specified from -40 °C to +85 °C
Nexperia
74AXP1G58
Low-power configurable multiple function gate
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74AXP1G58GM -40 °C to +85 °C
Name XSON6
74AXP1G58GN -40 °C to +85 °C
XSON6
74AXP1G58GS -40 °C to +85 °C
XSON6
74AXP1G58GX -40 °C to +85 °C
X2SON6
Description
plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm
extremely thin small outline package; no leads; 6 terminals; body 0.9 × 1.0 × 0.35 mm
extremely thin small outline package; no leads; 6 terminals; body 1.0 × 1.0 × 0.35 mm
plastic thermal enhanced extremely thin small outline package; no leads; 6 terminals; body 1.0 × 0.8 × 0.32 mm
Version SOT886 SOT1115 SOT1202 SOT1255-2
4. Marking
Table 2. Marking codes Type number 74AXP1G58GM 74AXP1G58GN 74AXP1G58GS 74AXP1G58GX
Marking code[1] RK RK RK RK
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
A3 B1 C6
Fig. 1. Logic symbol
4Y 001aab687
74AXP1G58
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 7 October 2021
© Nexperia B.V. 2021. All rights reserved
2 / 17
Nexperia
6. Pinning information
74AXP1G58
Low-power configurable multiple function gate
6.1. Pinning
74AXP1G58
B1
6C
GND 2
5 VCC
A3
4Y
aaa-008195 Transparent top view
Fig. 2. Pin configuration SOT886 (XSON6)
74AXP1G58
B
1
6
C
GND
2
5
VCC
A
3
4
Y
aaa-008196 Transparent top view
Fig. 3. Pin configuration SOT1115 and SOT1202 (XSON6)
74AXP1G58
B1
6C
GND
2
5
VCC
A3
4Y
aaa-019841 Transparent top view
Fig. 4. Pin configuration SOT1255-2 (X2SON6)
6.2. Pin description
Table 3. Pin description
Symbol
Pin
B
1
GND
2
A
3
Y
4
VCC
5
C
6
7. Functional description
Table 4. Function table H = HIGH voltage level; L = LOW voltage level.
Input
C
B
A
L
L
L
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
H
H
L
H
H
H
Description data input ground (0 V) data input data output supply voltage data input
Output Y L H L H H H L L
74AXP1G58
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 7 October 2021
© Nexperia B.V. 2021. All rights reserved
3 / 17
Nexperia
74AXP1G58
Low-power configurable multiple function gate
7.1. Logic configurations
Table 5. Function selection table Logic function 2-input NAND 2-input NAND with both inputs inverted 2-input AND with inverted input 2-input NOR with inverted input 2-input OR 2-input OR with both inputs inverted 2-input XOR Buffer Inverter
Figure see Fig. 5 see Fig. 8 see Fig. 6 and Fig. 7 see Fig. 6 and Fig. 7 see Fig. 8 see Fig. 5 see Fig. 9 see Fig. 10 see Fig. 11
VCC
B C
Y
B1
6C
2
5
B C
Y
3
4Y
001aab688
VCC
B C
Y
B1
6C
2
5
B C
Y
3
4Y
001aab689
Fig. 5. 2-input NAND gate or 2-input OR gate with both Fig. 6. 2-input AND gate with inverted B input or
inputs inverted
2-input NOR gate with inverted C input
VCC
A C
Y
1
6C
2
5
A C
Y
A3
4Y
001aab690
VCC
A C
Y
1
6C
2
5
A C
Y
A3
4Y
001aab691
Fig. 7. 2-input AND gate with inverted C input or 2-input NOR gate with inverted A input
Fig. 8. 2-input OR gate or 2-input NAND gate with both inputs inverted
VCC
VCC
B
1
6C
B C
Y
2
5
3
4Y
1
6
A
Y
2
5
A3
4Y
Fig. 9. 2-input XOR ga.