74HCT4075

74HC4075; 74HCT4075 Triple 3-input OR gate Rev. 4 — 4 February 2019 Product data sheet 1. General description The 74HC4075; 74HCT4075 is a triple 3-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits Complies with JEDEC standard no. 7A Input levels: For 74HC4075: CMOS level For 74HCT4075: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC4075D -40 °C to +125 °C 74HCT4075D Name SO14 Description plastic small outline package; 14 leads; body width 3.9 mm Version SOT108-1 4. Functional diagram 3 1A 4 1B 5 1C 1Y 6 1 2A 2 2B 8 2C 2Y 9 11 3A 12 3B 13 3C 3Y 10 aaa-024793 Fig. 1. Logic symbol 3 ≥1 46 5 1 ≥1 29 8 11 ≥1 12 10 13 aaa-024794 Fig. 2. IEC logic symbol A BY C aaa-024795 Fig. 3. Logic diagram (one gate) Nexperia 5. Pinning information 74HC4075; 74HCT4075 Triple 3-input OR gate 5.1. Pinning 74HC4075 74HCT4075 2A 1 2B 2 1A 3 1B 4 1C 5 1Y 6 GND 7 Fig. 4. Pin configuration SOT108-1 (SO14) 14 VCC 13 3C 12 3B 11 3A 10 3Y 9 2Y 8 2C aaa-024796 5.2. Pin description Table 2. Pin description Symbol 1A, 2A, 3A 1B, 2B, 3B 1C, 2C, 3C 1Y, 2Y, 3Y GND VCC Pin 3, 1, 11 4, 2, 12 5, 8, 13 6, 9, 10 7 14 6. Functional description Table 3. Fun...