Document
74LV7032A
Quad 2-input OR gate with Schmitt trigger inputs
Rev. 2 — 16 May 2023
Product data sheet
1. General description
The 74LV7032A is a quad 2-input OR function with Schmitt-trigger inputs, capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
2. Features and benefits
• Wide supply voltage range from 2.0 V to 5.5 V • Maximum tpd of 9.5 ns at 5 V • Typical VOL(p) < 0.8 V at VCC = 3.3 V, Tamb = 25 °C • Typical VOH(v) > 2.3 V at VCC = 3.3 V, Tamb = 25 °C • Supports mixed-mode voltage operation on all ports • IOFF circuitry provides partial Power-down mode operation • Latch-up performance exceeds 250 mA per JESD 78 Class II • ESD protection:
• MM: MM JESD22-A115-B exceeds 200 V • HBM: ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 4 kV • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 2 kV • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information Type number Package
Temperature range 74LV7032APW -40 °C to +125 °C
Name TSSOP14
Description
plastic thin shrink small outline package; 14 leads; body width 4.4 mm
Version SOT402-1
Nexperia
74LV7032A
Quad 2-input OR gate with Schmitt trigger inputs
4. Functional diagram
1 1A 2 1B
1Y 3
4 2A 5 2B
2Y 6
9 3A 10 3B
3Y 8
12 4A 13 4B
4Y 11
aaa-029455
Fig. 1. Logic symbol
1
≥1
3
2
4
≥1
6
5
9
≥1
8
10
12
≥1
11
13
aaa-029456
Fig. 2. IEC logic symbol
A Y
B
aaa-029457
Fig. 3. Logic diagram (one Schmitttrigger)
5. Pinning information
5.1. Pinning
PW package SOT402-1 (TSSOP14)
1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7
14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y
aaa - 03 6 071
5.2. Pin description
Table 2. Pin description Symbol 1A, 2A, 3A, 4A 1B, 2B, 3B, 4B 1Y, 2Y, 3Y, 4Y GND VCC
Pin 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14
Description data input data input data output ground (0 V) supply voltage
74LV7032A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 May 2023
© Nexperia B.V. 2023. All rights reserved
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Nexperia
74LV7032A
Quad 2-input OR gate with Schmitt trigger inputs
6. Functional description
Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Input
nA
nB
L
L
X
H
H
X
Output nY L H H
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max Unit
VCC
supply voltage
VI
input voltage
VO
output voltage
output HIGH or LOW state output power-down
-0.5 [1] -0.5 [2][3] -0.5 [2] -0.5
+7.0 V +.