74VHC02

74VHC02; 74VHCT02 Quad 2-input NOR gate Rev. 2 — 15 April 2020 Product data sheet 1. General description The 74VHC02; 74VHCT02 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7-A. The 74VHC02; 74VHCT02 provide a quad 2-input NOR function. 2. Features and benefits Balanced propagation delays All inputs have a Schmitt-trigger action Inputs accept voltages higher than VCC Input levels: The 74VHC02 operates with CMOS input level The 74VHCT02 operates with TTL input level ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74VHC02D -40 °C to +125 °C SO14 74VHCT02D 74VHC02PW -40 °C to +125 °C TSSOP14 74VHCT02PW 74VHC02BQ -40 °C to +125 °C DHVQFN14 74VHCT02BQ Description plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm Version SOT108-1 SOT402-1 SOT762-1 Nexperia 4. Functional diagram 2 1A 3 1B 5 2A 6 2B 8 3A 9 3B 11 4A 12 4B 1Y 1 2Y 4 3Y 10 4Y 13 mna216 Fig. 1. Logic symbol 2 ≥1 3 1 5 ≥1 6 4 ...