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74LVC1G79 Dataheets PDF



Part Number 74LVC1G79
Manufacturers nexperia
Logo nexperia
Description Single D-type flip-flop
Datasheet 74LVC1G79 Datasheet74LVC1G79 Datasheet (PDF)

74LVC1G79 Single D-type flip-flop; positive-edge trigger Rev. 14 — 29 March 2022 Product data sheet 1. General description The 74LVC1G79 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V en.

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74LVC1G79 Single D-type flip-flop; positive-edge trigger Rev. 14 — 29 March 2022 Product data sheet 1. General description The 74LVC1G79 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • Wide supply voltage range from 1.65 V to 5.5 V • Overvoltage tolerant inputs to 5.5 V • High noise immunity • CMOS low power dissipation • ±24 mA output drive (VCC = 3.0 V) • Direct interface with TTL levels • Latch-up performance exceeds 250 mA • IOFF circuitry provides partial Power-down mode operation • Complies with JEDEC standard: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8C (2.7 V to 3.6 V) • JESD36 (4.5 V to 5.5 V) • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • Multiple package options • Specified from -40 °C to +85 °C and -40 °C to +125 °C. Nexperia 74LVC1G79 Single D-type flip-flop; positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74LVC1G79GW -40 °C to +125 °C 74LVC1G79GV 74LVC1G79GM -40 °C to +125 °C -40 °C to +125 °C 74LVC1G79GN -40 °C to +125 °C 74LVC1G79GS -40 °C to +125 °C 74LVC1G79GX -40 °C to +125 °C Name TSSOP5 SC-74A XSON6 XSON6 XSON6 X2SON5 Description Version plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 plastic surface-mounted package; 5 leads SOT753 plastic extremely thin small outline package; SOT886 no leads; 6 terminals; body 1 × 1.45 × 0.5 mm extremely thin small outline package; no leads; SOT1115 6 terminals; body 0.9 × 1.0 × 0.35 mm extremely thin small outline package; no leads; SOT1202 6 terminals; body 1.0 × 1.0 × 0.35 mm plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 × 0.8 × 0.32 mm SOT1226-3 4. Marking Table 2. Marking codes Type number 74LVC1G79GW 74LVC1G79GV 74LVC1G79GM 74LVC1G79GN 74LVC1G79GS 74LVC1G79GX Marking[1] VP V79 VP VP VP VP [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1D Q4 2 CP Fig. 1. Logic symbol mna440 1D 2 CP Q4 mna441 Fig. 2. IEC logic symbol 74LVC1G79 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 29 March 2022 © Nexperia B.V. 2022. All rights reserved 2 / 19 Nexperia CP D Fig. 3. Logic diagram C C C TG C C TG C 6. Pinning information 74LVC1G79 Single D-type flip-flop; positive-edge trigger C TG C C TG C Q mna442 6.1. Pinning 74LVC1G79 D1 CP 2 5 VCC GND 3 4Q 001aaf188 Fig. 4. Pin configuration SOT353-1 (TSSOP5) and SOT753 (SC-74A) 74LVC1G79 D1 CP 2 6 VCC 5 n.c. GND 3 4Q 001aaf410 Transparent top view Fig. 6. Pin configuration SOT1115 and SOT1202 (XSON6) 74LVC1G79 D1 6 VCC CP 2 5 n.c. GND 3 4Q 001aaf189 Transparent top view Fig. 5. Pin configuration SOT886 (XSON6) 74LVC1G79 D1 3 GND 5 VCC CP 2 4Q aaa-003029 Transparent top view Fig. 7. Pin configuration SOT1226-3 (X2SON5) 74LVC1G79 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 29 March 2022 © Nexperia B.V. 2022. All rights reserved 3 / 19 Nexperia 74LVC1G79 Single D-type flip-flop; positive-edge trigger 6.2. Pin description Table 3. Pin description Symbol D CP GND Q n.c. VCC Pin TSSOP5, SC-74A and X2SON5 1 2 3 4 5 XSON6 1 2 3 4 5 6 Description data input clock pulse input ground (0 V) data output not connected supply voltage 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH CP transition; X = don’t care; q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition. Input Output CP D Q ↑ L L ↑ H H L X q 74LVC1G79 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 29 March 2022 © Nexperia B.V. 2022. All rights reserved 4 / 19 Nexperia 74LVC1G79 Single D-type flip-flop; positive-edge trigger 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC IIK VI IOK VO IO IC.


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