74LVT573

74LVT573 3.3 V octal D-type transparent latch; 3-state Rev. 9 — 30 July 2021 Product data sheet 1. General description The 74LVT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs 2. Features and benefits Wide supply voltage range from 2.7 to 3.6 V Inputs and outputs arranged for easy interfacing to microprocessors 3-state outputs for bus interfacing Common output enable control Overvoltage tolerant inputs to 5.5 V BiCMOS high speed and output drive Direct interface with TTL levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted No bus current loading when output is tied to 5 V bus Power-up reset Power-up 3-state IOFF circuitry provides partial Power-down mode operation Latch-up performance...