74AHCT594

74AHC594; 74AHCT594 8-bit shift register with output register Rev. 4 — 7 July 2021 Product data sheet 1. General description The 74AHC594; 74AHCT594 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC594; 74AHCT594 is an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct overriding clears (SHR and STR) are provided on both the shift and storage registers. A serial output (Q7S) is provided for cascading purposes. Both the shift and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one count pulse ahead of the storage register. 2. Features and benefits Wide supply voltage range from 2.0 V to 5.5 V Balanced propagation delays All inputs have Schmitt-trigger action Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation 8-bit serial-in, parallel-out shift register with storage Independent direct overriding clears on shift and storage registers Independent clocks for shift and storage registers Latch-up performance exceeds 100 mA per JESD 78 Class II Level A Input levels: For 74AHC594: CMOS level For 74AHCT594: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds ...