Document
74HC151; 74HCT151
8-input multiplexer
Rev. 10 — 19 October 2022
Product data sheet
1. General description
The 74HC151; 74HCT151 is an 8-bit multiplexer with eight binary inputs (I0 to I7), three select inputs (S0 to S2) and an enable input (E). One of the eight binary inputs is selected by the select inputs and routed to the complementary outputs (Y and Y). A HIGH on E forces the output Y LOW and output Y HIGH. Inputs also include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
• Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Input levels:
• For 74HC151: CMOS level • For 74HCT151: TTL level • Non-inverting data path • Complies with JEDEC standards • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.0 V) • ESD protection: • • HBM JESD22-A114F exceeds 2 kV • MM JESD22-A115-A exceeds 200 V • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74HC151D 74HCT151D
-40 °C to +125 °C
74HC151PW 74HCT151PW
-40 °C to +125 °C
74HC151BQ
-40 °C to +125 °C
Name
Description
SO16
plastic small outline package; 16 leads; body width 3.9 mm
TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm
DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm
Version SOT109-1
SOT403-1
SOT763-1
Nexperia
74HC151; 74HCT151
8-input multiplexer
4. Functional diagram
4 3 2 1 15 14 13 12
Fig. 1. Logic symbol
I0 I1 I2 I3 I4 I5 I6 I7
7E
Y5 Y6
S0
S1
S2
11
10
9
aaa-004582
I7
I6
I5
4 3 2 1 15 14 13 12
I4
I0 I1 I2 I3 I4 I5 I6 I7
I3
Y
11
S0
I2
Y
10
S1
MULTIPLEXER
I1
9
S2
I0
7
E
Y 5
Fig. 2. Functional diagram
Y aaa-004586
6
S2 S1 S0 E
Fig. 3. Logic diagram
aaa-004587
74HC_HCT151
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 19 October 2022
© Nexperia B.V. 2022. All rights reserved
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Nexperia
5. Pinning information
74HC151; 74HCT151
8-input multiplexer
5.1. Pinning
D package SOT109-1 (SO16)
BQ package SOT763-1 (DHVQFN16)
1 I3 16 VCC
I3 1 I2 2 I1 3 I0 4 Y5 Y6 E7 GND 8
16 VCC 15 I4 14 I5 13 I6 12 I7 11 S0 10 S1 9 S2 aaa-035627
PW package SOT403-1 (TSSOP16)
I3 1 I2 2 I1 3 I0 4 Y5 Y6 E7 GND 8
16 VCC 15 I4 14 I5 13 I6 12 I7 11 S0 10 S1 9 S2
aaa-035628
terminal 1 index area
I2 2 I1 3 I0 4 Y5 Y6 E7
GND(1)
15 I4 14 I5 13 I6 12 I7 11 S0 10 S1
GND 8 S2 9
aaa-035629 Transparent top view
(1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND.
5.2. Pin description
Table 2. Pin description Symbol I0, I1, I2, I3, I4, I5, I6, I7 Y Y E GND S0, S1, .