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74AHC3GU04 Dataheets PDF



Part Number 74AHC3GU04
Manufacturers nexperia
Logo nexperia
Description Triple unbuffered inverter
Datasheet 74AHC3GU04 Datasheet74AHC3GU04 Datasheet (PDF)

74AHC3GU04 Triple unbuffered inverter Rev. 6 — 27 February 2019 Product data sheet 1. General description The 74AHC3GU04 is a high-speed Si-gate CMOS device. This device provides three inverter gates with unbuffered outputs. 2. Features and benefits • Symmetrical output impedance • High noise immunity • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101D exceeds 1000 V • Low power dissipation • Balanced propagation delays • Specified from -40 .

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74AHC3GU04 Triple unbuffered inverter Rev. 6 — 27 February 2019 Product data sheet 1. General description The 74AHC3GU04 is a high-speed Si-gate CMOS device. This device provides three inverter gates with unbuffered outputs. 2. Features and benefits • Symmetrical output impedance • High noise immunity • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101D exceeds 1000 V • Low power dissipation • Balanced propagation delays • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74AHC3GU04DP -40 °C to +125 °C 74AHC3GU04DC -40 °C to +125 °C Name TSSOP8 VSSOP8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm plastic very thin shrink small outline package; 8 leads; body width 2.3 mm Version SOT505-2 SOT765-1 4. Marking Table 2. Marking codes Type number 74AHC3GU04DP 74AHC3GU04DC Marking code [1] AU4 AU4 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. Nexperia 5. Functional diagram 11 7 1 1A 1Y 7 3 2A 2Y 5 6 3A 3Y 2 mna720 Fig. 1. Logic symbol 31 5 61 2 mna721 Fig. 2. IEC logic symbol 6. Pinning information 74AHC3GU04 Triple unbuffered inverter AY mna045 Fig. 3. Logic diagram (one gate) 6.1. Pinning 74AHC3GU04 1A 3Y 2A GND 1 2 3 4 8 VCC 7 1Y 6 3A 5 2Y 001aaj517 Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 6.2. Pin description Table 3. Pin description Symbol 1A, 2A, 3A GND 1Y, 2Y, 3Y VCC Pin 1, 3, 6 4 7, 5, 2 8 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level Input A L H Output Y H L Description data input ground (0 V) data output supply voltage 74AHC3GU04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 27 February 2019 © Nexperia B.V. 2019. All rights reserved 2 / 13 Nexperia 74AHC3GU04 Triple unbuffered inverter 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC VI IIK IOK IO ICC IGND Tstg Ptot supply voltage input voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation VI < -0.5 V VO < -0.5 V or VO > VCC + 0.5 V -0.5 V < VO < VCC + 0.5 V Tamb = -40 °C to +125 °C -0.5 -0.5 [1] -20 [1] - -75 -65 [2] - +7.0 +7.0 ±20 ±25 75 +150 250 V V mA mA mA mA mA °C mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. 9. Recommended operating conditions Table 6. Recommended .


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