74HC2G34

74HC2G34; 74HCT2G34 Dual buffer gate Rev. 2 — 3 February 2022 Product data sheet 1. General description The 74HC2G34; 74HCT2G34 is a dual buffer. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V High noise immunity CMOS low power dissipation Balanced propagation delays Unlimited input rise and fall times Input levels: For 74HC2G34: CMOS level For 74HCT2G34: TTL level Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: HBM JESD22-A114-D exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74HC2G34GW -40 °C to +125 °C TSSOP6 74HCT2G34GW 74HC2G34GV 74HCT2G34GV -40 °C to +125 °C SC-74; TSOP6 Description plastic thin shrink small outline package; 6 leads; body width 1.25 mm plastic surface-mounted package; 6 leads Version SOT363-2 SOT457 Nexperia 74HC2G34; 74HCT2G34 Dual buffer gate 4. Marking Table 2. Marking Type number 74HC2G34GW 74HCT2G34GW 74HC2G34GV 74HCT2G34GV Marking code[1] PA UA P34 U34 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1A 1Y 6 3 ...