74LVC3G16

74LVC3G16 Triple buffer Rev. 3 — 12 May 2021 Product data sheet 1. General description The 74LVC3G16 provides three buffers. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC3G16 as a translator in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LVC3G16DP -40 °C to +125 °C TSSOP8 74LVC3G16GF -40 °C to +125 °C XSON8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1 × 0.5 mm Version SOT505-2 SOT1089 Nexperia 74LVC3G16 Triple buffer 4. Mar...