74VHC125

74VHC125; 74VHCT125 Quad buffer/line driver; 3-state Rev. 3 — 8 April 2020 Product data sheet 1. General description The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74VHC125; 74VHCT125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state. The 74VHC125; 74VHCT125 are identical to the 74VHC126; 74VHCT126 but have active LOW enable inputs. 2. Features and benefits Balanced propagation delays All inputs have a Schmitt-trigger action Inputs accepts voltages higher than VCC Input levels: The 74VHC125 operates with CMOS logic levels The 74VHCT125 operates with TTL logic levels ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74VHC125D -40 °C to +125 °C 74VHCT125D 74VHC125PW -40 °C to +125 °C 74VHCT125PW 74VHC125BQ -40 °C to +125 °C 74VHCT125BQ Name SO14 Description plastic small outline package; 14 leads; body width 3.9 mm TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm DHVQFN14 plasti...