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74AHC86-Q100 Dataheets PDF



Part Number 74AHC86-Q100
Manufacturers nexperia
Logo nexperia
Description Quad 2-input EXCLUSIVE-OR gate
Datasheet 74AHC86-Q100 Datasheet74AHC86-Q100 Datasheet (PDF)

74AHC86-Q100; 74AHCT86-Q100 Quad 2-input EXCLUSIVE-OR gate Rev. 2 — 5 June 2020 Product data sheet 1. General description The 74AHC86-Q100; 74AHCT86-Q100 is a quad 2-input EXCLUSIVE-OR gate. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • Au.

  74AHC86-Q100   74AHC86-Q100



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74AHC86-Q100; 74AHCT86-Q100 Quad 2-input EXCLUSIVE-OR gate Rev. 2 — 5 June 2020 Product data sheet 1. General description The 74AHC86-Q100; 74AHCT86-Q100 is a quad 2-input EXCLUSIVE-OR gate. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C • Wide supply voltage range from 2.0 V to 5.5 V • Input levels: • For 74AHC86-Q100: CMOS level • For 74AHCT86-Q100: TTL level • Balanced propagation delays • All inputs have Schmitt-trigger actions • Overvoltage tolerant inputs to 5.5 V • High noise immunity • CMOS low power dissipation • ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) • Latch-up performance exceeds 100 mA per JESD 78 Class II Level A • Multiple package options • DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC86D-Q100 74AHCT86D-Q100 -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74AHC86PW-Q100 -40 °C to +125 °C 74AHCT86PW-Q100 TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm 74AHC86BQ-Q100 -40 °C to +125 °C 74AHCT86BQ-Q100 DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm SOT762-1 Nexperia 4. Functional diagram Fig. 1. Logic symbol A B Fig. 2. Logic diagram (one gate) 74AHC86-Q100; 74AHCT86-Q100 Quad 2-input EXCLUSIVE-OR gate 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 3 2Y 6 3Y 8 4Y 11 mna787 Y mna788 1 =1 3 2 4 =1 6 5 9 =1 8 10 12 =1 11 13 Fig. 3. IEC logic symbol mna786 74AHC_AHCT86_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 5 June 2020 © Nexperia B.V. 2020. All rights reserved 2 / 14 Nexperia 5. Pinning information 5.1. Pinning 74AHC86 74AHCT86 1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y 001aah083 Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) 5.2. Pin description Table 2. Pin description Symbol 1A, 2A, 3A, 4A 1B, 2B, 3B, 4B 1Y, 2Y, 3Y, 4Y GND VCC Pin 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level. Input nA Input nB L L L H H L H H 74AHC86-Q100; 74AHCT86-Q100 Quad 2-input EXCLUSIVE-OR gate 74AHC86 74AHCT86 1 1A 14 VCC terminal 1 index area 1B 2 1Y 3 2.


74AHCT74-Q100 74AHC86-Q100 74AHCT86-Q100


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