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160V Dataheets PDF



Part Number 160V
Manufacturers Lattice Semiconductor
Logo Lattice Semiconductor
Description In-System Programmable 3.3V Generic Digital CrosspointTM
Datasheet 160V Datasheet160V Datasheet (PDF)

ispGDX 160V/VA TM In-System Programmable 3.3V Generic Digital Crosspoint TM Features • IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY — Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement — “Any Input to Any Output” Routing — Fixed HIGH or LOW Output Option for Jumper/DIP Switch Emulation — Space-Saving PQFP and BGA Packaging — Dedicated IEEE 1149.1-Compliant Boundary Scan Test • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — .

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ispGDX 160V/VA TM In-System Programmable 3.3V Generic Digital Crosspoint TM Features • IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY — Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement — “Any Input to Any Output” Routing — Fixed HIGH or LOW Output Option for Jumper/DIP Switch Emulation — Space-Saving PQFP and BGA Packaging — Dedicated IEEE 1149.1-Compliant Boundary Scan Test • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 3.3V Core Power Supply — 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay* — 250MHz Maximum Clock Frequency* — TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels (Individually Programmable)* — Low-Power: 16.5mA Quiescent Icc* — 24mA IOL Drive with Programmable Slew Rate Control Option — PCI Compatible Drive Capability* — Schmitt Trigger Inputs for Noise Immunity — Electrically Erasable and Reprogrammable — Non-Volatile E2CMOS Technology • ispGDXV™ OFFERS THE FOLLOWING ADVANTAGES — 3.3V In-System Programmable Using Boundary Scan Test Access Port (TAP) — Change Interconnects in Seconds • FLEXIBLE ARCHITECTURE — Combinatorial/Latched/Registered Inputs or Outputs — Individual I/O Tri-state Control with Polarity Control — Dedicated Clock/Clock Enable Input Pins (four) or Programmable Clocks/Clock Enables from I/O Pins (40) — Single Level 4:1 Dynamic Path Selection (Tpd = 3.5ns) — Programmable Wide-MUX Cascade Feature Supports up to 16:1 MUX — Programmable Pull-ups, Bus Hold Latch and Open Drain on I/O Pins — Outputs Tri-state During Power-up (“Live Insertion” Friendly) • DESIGN SUPPORT THROUGH LATTICE’S ispGDX DEVELOPMENT SOFTWARE — MS Windows or NT / PC-Based or Sun O/S — Easy Text-Based Design Entry — Automatic Signal Routing — Program up to 100 ISP Devices Concurrently — Simulator Netlist Generation for Easy Board-Level Simulation * “VA” Version Only Functional Block Diagram I/O Pins D ISP Control I/O Pins C I/O Pins A I/O Cells Global Routing Pool (GRP) I/O Cells Boundary Scan Control I/O Pins B Description The ispGDXV/VA architecture provides a family of fast, flexible programmable devices to address a variety of system-level digital signal routing and interface requirements including: • Multi-Port Multiprocessor Interfaces • Wide Data and Address Bus Multiplexing (e.g. 16:1 High-Speed Bus MUX) • Programmable Control Signal Routing (e.g. Interrupts, DMAREQs, etc.) • Board-Level PCB Signal Routing for Prototyping or Programmable Bus Interfaces The devices feature fast operation, with input-to-output signal delays (Tpd) of 3.5ns and clock-to-output delays of 3.5ns. The architecture of the devices consists of a series of programmable I/O cells interconnected by a Global Routing Pool (GRP). All I/O pin inputs enter the GRP directly or are registered or latched so they can be routed to the required I/O outputs. I/O pin inputs are defined as four sets (A,B,C,D) which have access to the four MUX inputs Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com July 2000 gdx160va_04 1 Specifications ispGDX160V/VA Description (Continued) found in each I/O cell. Each output has individual, programmable I/O tri-state control (OE), output latch clock (CLK), clock enable (CLKEN), and two multiplexer control (MUX0 and MUX1) inputs. Polarity for these signals is programmable for each I/O cell. The MUX0 and MUX1 inputs control a fast 4:1 MUX, allowing dynamic selection of up to four signal sources for a given output. A wider 16:1 MUX can be implemented with the MUX expander feature of each I/O and a propagation delay increase of 2.0ns. OE, CLK, CLKEN, and MUX0 and MUX1 inputs can be driven directly from selected sets of I/O pins. Optional dedicated clock input pins give minimum clockto-output delays. CLK and CLKEN share the same set of I/O pins. CLKEN disables the register clock when CLKEN = 0. Through in-system programming, connections between I/O pins and architectural features (latched or registered inputs or outputs, output enable control, etc.) can be defined. In keeping with its data path application focus, the ispGDXV devices contain no programmable logic arrays. All input pins include Schmitt trigger buffers for noise immunity. These connections are programmed into the device using non-volatile E2CMOS technology. Non-volatile technology means the device configuration is saved even when the power is removed from the device. Table 1. ispGDXV Family Members ispGDXV/VA Device ispGDX80VA I/O Pins I/O-OE Inputs* I/O-CLK / CLKEN Inputs* I/O-MUXsel1 Inputs* I/O-MUXsel2 Inputs* Dedicated Clock Pins** EPEN TOE BSCAN Interface RESET Pin Count/Package 80 20 20 20 20 2 1 1 4 1 100.


1602H 160V 1617-35


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