Document
PHP29N08T
N-channel TrenchMOS standard level FET
Rev. 02 — 12 March 2009
Product data sheet
1. Product profile
1.1 General description
Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
High noise immunity due to high gate threshold voltage
Low conduction losses due to low on-state resistance
1.3 Applications
Industrial motor control
1.4 Quick reference data
Table 1. Quick reference
Symbol VDS ID
Parameter drain-source voltage drain current
Conditions
Tj ≥ 25 °C; Tj ≤ 175 °C
Tmb = 25 °C; VGS = 11 V; see Figure 1; see Figure 3
Ptot total power dissipation
Tmb = 25 °C; see Figure 2
Dynamic characteristics
QGD
gate-drain charge
VGS = 10 V; ID = 29 A; VDS = 60 V; Tj = 25 °C; see Figure 11
Static characteristics
RDSon
drain-source on-state resistance
VGS = 11 V; ID = 14 A; Tj = 175 °C; see Figure 9; see Figure 10
VGS = 11 V; ID = 14 A; Tj = 25 °C; see Figure 9; see Figure 10
Min Typ Max Unit - - 75 V - - 27 A - - 88 W
- 9 - nC
- 96 120 mΩ
- 40 50 mΩ
Nexperia
2. Pinning information
Table 2. Pinning information
Pin Symbol Description
1G
gate
2D
drain
3S
source
mb D
mounting base, connected to drain
PHP29N08T
N-channel TrenchMOS standard level FET
Simplified outline
mb
Graphic symbol
D
G mbb076 S
3. Ordering information
123
SOT78 (TO-220AB; SC-46)
Table 3. Ordering information
Type number
Package
Name
Description
PHP29N08T
TO-220AB; plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead
SC-46
TO-220AB
Version SOT78
4. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol VDS VDGR VGS ID
Parameter drain-source voltage drain-gate voltage gate-source voltage drain current
IDM peak drain current Ptot total power dissipation Tstg storage temperature Tj junction temperature Source-drain diode
Conditions Tj ≥ 25 °C; Tj ≤ 175 °C Tj ≤ 175 °C; Tj ≥ 25 °C; RGS = 20 kΩ
VGS = 11 V; Tmb = 100 °C; see Figure 1 VGS = 11 V; Tmb = 25 °C; see Figure 1; see Figure 3 tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3 Tmb = 25 °C; see Figure 2
IS source current Tmb = 25 °C ISM peak source current tp ≤ 10 µs; pulsed; Tmb = 25 °C
Min Max Unit
- 75 V
- 75 V
-30 30
V
- 19.2 A
- 27 A
- 108 A - 88 W -55 175 °C -55 175 °C
- 27 A - 108 A
PHP29N08T_2
Product data sheet
Rev. 02 — 12 March 2009
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120 Ider (%)
80
03aa24
PHP29N08T
N-channel TrenchMOS standard level FET
120
Pder (%)
80
03aa16
40 40
0 0 50 100 150 200 Tmb (°C)
0 0 50 100 150 200 Tmb (°C)
Fig 1. Normalized continuous drain current as a function of mounting base temperature
103
ID (A)
102
Limit RDSon = VDS/ID
10
1 1
DC 10
Fig 2. Normalized total power dissipation as a function of mounting base temperature
03aj06
tp = 10 μs 100 μs 1 ms
102
VDS (V)
103
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHP29N08T_2
Product data sheet
Rev. 02 — 12 March 2009
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© Nexperia B.V. 2017. All rights reserved
Nexperia
PHP29N08T
N-channel TrenchMOS standard level FET
5. Thermal characteristics
Table 5. Symbol Rth(j-mb)
Rth(j-a)
Thermal characteristics
Parameter
Conditions
thermal resistance from see Figure 4 junction to mounting base
thermal resistance from vertical in still air junction to ambient
Min Typ Max Unit - - 1.7 K/W
- 60 - K/W
1
Zth(j-mb) (K/W)
δ = 0.5 0.2
10−1
0.1
0.05 0.02
single pulse
03aj05 P δ = tp
T
10−2 10−4
10−3
10−2
10−1
tp T
tp (s)
t 1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PHP29N08T_2
Product data sheet
Rev. 02 — 12 March 2009
4 of 12
© Nexperia B.V. 2017. All rights reserved
Nexperia
PHP29N08T
N-channel TrenchMOS standard level FET
6. Characteristics
Table 6. Characteristics
Symbol Parameter
Static characteristics
V(BR)DSS drain-source breakdown voltage
VGS(th)
gate-source threshold voltage
IDSS IGSS RDSon
drain leakage current
gate leakage current
drain-source on-state resistance
Dynamic characteristics
QG(tot) QGS QGD Ciss Coss Crss
total gate charge gate-source charge gate-drain charge input capacitance output capacitance reverse transfer capacitance
td(on)
turn-on delay time
tr rise time
td(off)
turn-off delay time
tf fall time
Source-drain diode
VSD source-drain voltage
trr reverse recovery time Qr recovered charge
Conditions
ID = 0.25 mA; VGS = 0 V; Tj = -55 °C ID = 0.25 mA; VGS = 0 V; Tj = 25 °C ID = 2 mA; VDS = VGS; Tj = 175 °C; see Figure 8 ID = 2 mA; VDS = VGS; Tj = -55 °C; see Figure 8 ID = 2 mA; VDS = VGS; Tj = 25 °C; see Figure 8 VDS = 75 V; VGS = 0 V; Tj = 25 °C VDS = 75 V; VGS = 0 V; Tj = .