PSMN2R5-40YLD

PSMN2R5-40YLD 40 V logic level MOSFET 8 July 2019 Preliminary data sheet 1. General description Logic level gate drive N-channel enhancement mode MOSFET. 2. Quick reference data Table 1. Quick reference data Symbol Parameter VDS drain-source voltage ID drain current Ptot total power dissipation Tj junction temperature Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD gate-drain charge QG(tot) total gate charge Conditions 25 °C ≤ Tj ≤ 175 °C VGS = 10 V; Tmb = 25 °C; Fig. 2 Tmb = 25 °C; Fig. 1 VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 10 VGS = 4.5 V; ID = 25 A; Tj = 25 °C; Fig. 10 ID = 25 A; VDS = 20 V; VGS = 4.5 V; Fig. 12; Fig. 13 Min Typ Max Unit - - 40 V [1] - - 120 A - - 147 W -55 - 175 °C - 2.2 2.5 mΩ - 2.7 3.3 mΩ - 5.9 11.8 nC - 25 35 nC [1] 120A Continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. 3. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1S source mb 2S source 3S source 4G gate mb D mounting base; connected to drain 1234 LFPAK56; PowerSO8 (SOT669) Graphic symbol D G mbb076 S Nexperia PSMN2R5-40YLD 40 V logic level MOSFET 4. Ordering information Table 3. Ordering information Type number Package Name PSMN2R5-40YLD LFPAK56; Power-SO8 Description plastic, single-ended surface-mounted package; 4 terminals Version S...