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PSMN9R1-30YL Dataheets PDF



Part Number PSMN9R1-30YL
Manufacturers nexperia
Logo nexperia
Description N-channel MOSFET
Datasheet PSMN9R1-30YL DatasheetPSMN9R1-30YL Datasheet (PDF)

PSMN9R1-30YL N-channel 9.1 mΩ 30 V TrenchMOS logic level FET in LFPAK Rev. 2 — 16 May 2011 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in industrial and communications applications. 1.2 Features and benefits „ High efficiency due to low switching and conduction losses „ Suitable for logic level gate drive sou.

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PSMN9R1-30YL N-channel 9.1 mΩ 30 V TrenchMOS logic level FET in LFPAK Rev. 2 — 16 May 2011 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in industrial and communications applications. 1.2 Features and benefits „ High efficiency due to low switching and conduction losses „ Suitable for logic level gate drive sources 1.3 Applications „ Class-D amplifiers „ DC-to-DC converters „ Motor control „ Server power supplies 1.4 Quick reference data Table 1. Symbol VDS ID Quick reference data Parameter drain-source voltage drain current Ptot total power dissipation Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD gate-drain charge QG(tot) total gate charge Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy Conditions Tj ≥ 25 °C; Tj ≤ 175 °C Tmb = 25 °C; VGS = 10 V; see Figure 1 Tmb = 25 °C; see Figure 2 VGS = 10 V; ID = 15 A; Tj = 25 °C VGS = 10 V; ID = 45 A; VDS = 15 V; see Figure 14; see Figure 15 VGS = 4.5 V; ID = 45 A; VDS = 15 V; see Figure 14; see Figure 15 VGS = 10 V; Tj(init) = 25 °C; ID = 57 A; Vsup ≤ 30 V; RGS = 50 Ω; unclamped Min Typ Max Unit - - 30 V - - 57 A - - 52 W - 7.8 9.1 mΩ - 4.1 - nC - 8.4 - nC - - 17 mJ Nexperia PSMN9R1-30YL N-channel 9.1 mΩ 30 V TrenchMOS logic level FET in LFPAK 2. Pinning information Table 2. Pin 1 2 3 4 mb Pinning information Symbol Description S source S source S source G gate D mounting base; connected to drain Simplified outline mb 1234 SOT669 (LFPAK; Power-SO8) 3. Ordering information Graphic symbol D G mbb076 S Table 3. Ordering information Type number Package Name PSMN9R1-30YL LFPAK; Power-SO8 4. Limiting values Description plastic single-ended surface-mounted package; 4 leads Version SOT669 Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDS VDSM VDGR VGS ID IDM Parameter drain-source voltage peak drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current Conditions Tj ≥ 25 °C; Tj ≤ 175 °C tp ≤ 25 ns; f ≤ 500 kHz; EDS(AL) ≤ 60 nJ; pulsed Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ VGS = 10 V; Tmb = 100 °C; see Figure 1 VGS = 10 V; Tmb = 25 °C; see Figure 1 pulsed; tp ≤ 10 µs; Tmb = 25 °C; see Figure 3 Ptot total power dissipation Tstg storage temperature Tj junction temperature Source-drain diode Tmb = 25 °C; see Figure 2 IS source current ISM peak source current Avalanche ruggedness Tmb = 25 °C pulsed; tp ≤ 10 µs; Tmb = 25 °C EDS(AL)S non-repetitive drain-source avalanche energy VGS = 10 V; Tj(init) = 25 °C; ID = 57 A; Vsup ≤ 30 V; RGS = 50 Ω; unclamped Min Max Unit - 30 V - 35 V - 30 V -20 20 V - 40 A - 57 A - 229 A - 52 W -55 175 °C -55 175 °C - 57 A - 229 A - 17 mJ PSMN9R1-30YL Product data sheet All information provided in this docum.


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