Low-power D-type flip-flop
74AUP1G175-Q100
Low-power D-type flip-flop with reset; positive-edge trigger
Rev. 4 — 18 January 2022
Product data sh...
Description
74AUP1G175-Q100
Low-power D-type flip-flop with reset; positive-edge trigger
Rev. 4 — 18 January 2022
Product data sheet
1. General description
The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. A LOW on MR causes the flip-flop and output to be reset to LOW. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 0.8 V to 3.6 V CMOS low power dissipation High noise immunity Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V...
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