Document
74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
Rev. 2 — 4 February 2021
Product data sheet
1. General description
The 74HC175-Q100; 74HCT175-Q100 are quad positive edge-triggered D-type flip-flops with individual data inputs (Dn) and both Qn and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW.
The device is useful for applications where both the true and complement outputs are required and the clock and master reset are common to all storage elements.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
• Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Input levels: • For 74HC175-Q100: CMOS level • For 74HCT175-Q100: TTL level
• Four edge-triggered D-type flip-flops • Asynchronous master reset • Complies with JEDEC standard no. 7A • ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74HC175D-Q100 -40 °C to +125 °C
74HCT175D-Q100
74HC175PW-Q100 -40 °C to +125 °C
74HCT175PW-Q100
Name SO16
TSSOP16
Description
plastic small outline package; 16 leads; body width 3.9 mm
Version SOT109-1
plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm
Nexperia
74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
4. Functional diagram
9
4
CP Q0 D0
Q0
2 3
5 D1
Q1 7 Q1 6
12 D2
Q2 10 11
Q2
13
Q3 D3
MR Q3
15 14
1 aaa-008921
Fig. 1. Logic symbol
D0
D1
9
C1
1R
4 1D 5 12
13
Fig. 2. IEC logic symbol
D2
D3
2 3 7 6 10 11 15 14
aaa-008922
CP MR
Fig. 3. Logic diagram
DQ
CP FF1 Q
RD
DQ
CP FF2 Q
RD
DQ
CP FF3 Q
RD
DQ
CP FF4 Q
RD
Q0 Q0
Q1 Q1
Q2 Q2
Q3 Q3 aaa-008927
74HC_HCT175_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 February 2021
© Nexperia B.V. 2021. All rights reserved
2 / 16
Nexperia
5. Pinning information
74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
5.1. Pinning
74HC175 74HCT175
MR 1
16 VCC
Q0 2
15 Q3
Q0 3
14 Q3
D0 4
13 D3
D1 5
12 D2
Q1 6
11 Q2
Q1 7
10 Q2
GND 8
9 CP
aaa-008929
Fig. 4. Pin configuration SOT109-1 (SO16)
74HC175 74HCT175
MR 1 Q0 2 Q0 3 D0 4 D1 5 Q1 6 Q1 7 GND 8
16 VCC 15 Q3 14 Q3 13 D3 12 D2 11 Q2 10 Q2 9 CP
aaa-008930
Fig. 5. Pin configuration SOT403-1 (TSSOP16)
5.2. Pin description
Table 2. Pin description
Symbol
Pin
MR
1
Q0 to Q3
2, 7, 10, 15
Q0 to Q3
3, 6, 11, 14
D0 to D3
4, 5, 12, 13
GND
8
CP
9
VCC
16
Description asynchronous master reset input (active LOW) flip-flop output complementary flip-flop output data input ground (0 V) clock input (LOW-to-HIGH edge-triggered) positive supply voltage
6. Functional description
Table 3. Function table H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; X = don’t care; ↑ = LOW-to-HIGH clock transition.
Operating modes
Inputs
Outputs
MR
CP
Dn
Qn
Qn
reset (clear)
L
X
X
L
H
load "1"
H
↑
h
H
L
load "0"
H
↑
l
L
H
74HC_HCT175_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 February 2021
© Nexperia B.V. 2021. All rights reserved
3 / 16
Nexperia
74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
4
5
12
13
D0
D1
D2
D3
9 CP 1 MR
DQ
CP FF1 Q
RD
DQ
CP FF2 Q
RD
DQ
CP FF3 Q
RD
DQ
CP FF4 Q
RD
Q0 Q0 32
Q1 Q1 67
Q2 Q2 11 10
Q3 Q3 14 15
Fig. 6. Functional diagram
aaa-008931
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
Min
Max Unit
VCC IIK IOK IO ICC IGND Tstg Ptot
supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation
-0.5
VI < -0.5 V or VI > VCC + 0.5 V
-
VO < -0.5 V or VO > VCC + 0.5 V
-
-0.5 V < VO < VCC + 0.5 V
-
-
-50
-65
Tamb = -40 °C to +125 °C
[1]
-
+7
V
±20 mA
±20 mA
±25 mA
50
mA
-
mA
+150 °C
500 mW
[1] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C. For SOT403-1 (TSSOP16) package:.