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74HCT4053-Q100 Dataheets PDF



Part Number 74HCT4053-Q100
Manufacturers nexperia
Logo nexperia
Description Triple 2-channel analog multiplexer/demultiplexer
Datasheet 74HCT4053-Q100 Datasheet74HCT4053-Q100 Datasheet (PDF)

74HC4053-Q100; 74HCT4053-Q100 Triple 2-channel analog multiplexer/demultiplexer Rev. 3 — 5 March 2020 Product data sheet 1. General description The 74HC4053-Q100; 74HCT4053-Q100 is a triple single-pole double-throw analog switch (3x SPDT) suitable for use in analog or digital 2:1 multiplexer/demultiplexer applications. Each switch features a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). A digital enable input (E) is common to all swi.

  74HCT4053-Q100   74HCT4053-Q100


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74HC4053-Q100; 74HCT4053-Q100 Triple 2-channel analog multiplexer/demultiplexer Rev. 3 — 5 March 2020 Product data sheet 1. General description The 74HC4053-Q100; 74HCT4053-Q100 is a triple single-pole double-throw analog switch (3x SPDT) suitable for use in analog or digital 2:1 multiplexer/demultiplexer applications. Each switch features a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). A digital enable input (E) is common to all switches. When E is HIGH, the switches are turned off. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C • Wide analog input voltage range from -5 V to +5 V • Low ON resistance: • 80 Ω (typical) at VCC - VEE = 4.5 V • 70 Ω (typical) at VCC - VEE = 6.0 V • 60 Ω (typical) at VCC - VEE = 9.0 V • Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals • Typical ‘break before make’ built-in • ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) • CDM AEC-Q100-011 revision B exceeds 1000 V • Multiple package options • DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Applications • Analog multiplexing and demultiplexing • Digital multiplexing and demultiplexing • Signal gating Nexperia 74HC4053-Q100; 74HCT4053-Q100 Triple 2-channel analog multiplexer/demultiplexer 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4053D-Q100 74HCT4053D-Q100 -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC4053PW-Q100 -40 °C to +125 °C 74HCT4053PW-Q100 TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74HC4053BQ-Q100 -40 °C to +125 °C 74HCT4053BQ-Q100 DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm SOT763-1 5. Functional diagram E VCC 6 16 S1 11 LOGIC LEVEL CONVERSION DECODER 13 1Y1 12 1Y0 14 1Z S2 10 LOGIC LEVEL CONVERSION 1 2Y1 2 2Y0 15 2Z S3 9 LOGIC LEVEL CONVERSION 8 GND Fig. 1. Functional diagram 3 3Y1 5 3Y0 7 VEE 4 3Z 001aak341 74HC_HCT4053_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 5 March 2020 © Nexperia B.V. 2020. All rights reserved 2 / 25 Nexperia 11 S1 10 S2 9 S3 6E Fig. 2. Logic symbol 1Y0 12 1Y1 13 1Z 14 2Y0 2 2Y1 1 2Z 15 3Y0 5 3Y1 3 3Z 4 001aae125 from logic Fig. 4. Schematic diagram (one switch) 74HC4053-Q100; 74HCT4053-Q100 Triple 2-channel analog multiplexer/demultiplexer 6 EN MUX/DMUX 11 # × 0 1 14 0/1 0 12 1 13 10 # 2 15 1 9# 5 4 3 001aae126 Fig. 3. IEC logic symbol Y VCC VEE VCC VEE VCC VCC VEE Z 001aad544 74HC_HCT4053_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 5 March 2020 © Nexperia B.V. 2020. All rights reserved 3 / 25 Nexperia 74HC4053-Q100; 74HCT4053-Q100 Triple 2-channel analog multiplexer/demultiplexer 6. Pinning information 6.1. Pinning 74HC4053-Q100 74HCT4053-Q100 2Y1 1 2Y0 2 3Y1 3 3Z 4 3Y0 5 E6 VEE 7 GND 8 16 VCC 15 2Z 14 1Z 13 1Y1 12 1Y0 11 S1 10 S2 9 S3 aaa-003164 Fig. 5. Pin configuration SOT109-1 (SO16) and SOT403-1 (TSSOP16) 74HC4053-Q100 74HCT4053-Q100 terminal 1 index area 1 2Y1 16 VCC 2Y0 2 3Y1 3 3Z 4 3Y0 5 E6 VEE 7 VCC(1) 15 2Z 14 1Z 13 1Y1 12 1Y0 11 S1 10 S2 GND 8 S3 9 aaa-003165 Fig. 6. Transparent top view (1) This is not a supply pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to VCC. Pin configuration SOT763-1 (DHVQFN16) 6.2. Pin description Table 2. Pin description Symbol E VEE GND S1, S2, S3 1Y0, 2Y0, 3Y0 1Y1, 2Y1, 3Y1 1Z, 2Z, 3Z VCC Pin 6 7 8 11, 10, 9 12, 2, 5 13, 1, 3 14, 15, 4 16 7. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care. Inputs E Sn L L L H H X Description enable input (active LOW) supply voltage ground supply voltage select input independent input or output independent input or output common output or input supply voltage Channel on nY0 to nZ nY1 to nZ switches off 74HC_HCT4053_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 5 March 2020 © Nexperia B.V. 2020. All r.


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