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74HCT573-Q100 Dataheets PDF



Part Number 74HCT573-Q100
Manufacturers nexperia
Logo nexperia
Description Octal D-type transparent latch
Datasheet 74HCT573-Q100 Datasheet74HCT573-Q100 Datasheet (PDF)

74HC573-Q100; 74HCT573-Q100 Octal D-type transparent latch; 3-state Rev. 6 — 10 February 2021 Product data sheet 1. General description The 74HC573-Q100; 74HCT573-Q100 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches .

  74HCT573-Q100   74HCT573-Q100



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74HC573-Q100; 74HCT573-Q100 Octal D-type transparent latch; 3-state Rev. 6 — 10 February 2021 Product data sheet 1. General description The 74HC573-Q100; 74HCT573-Q100 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C • Input levels: • For 74HC573-Q100: CMOS level • For 74HCT573-Q100: TTL level • Inputs and outputs on opposite sides of package allowing easy interface with microprocessors • Useful as input or output port for microprocessors and microcomputers • 3-state non-inverting outputs for bus-oriented applications • Common 3-state output enable input • Multiple package options • ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2 000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) • DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74HC573D-Q100 -40 °C to +125 °C SO20 74HCT573D-Q100 74HC573PW-Q100 -40 °C to +125 °C TSSOP20 74HCT573PW-Q100 74HC573BQ-Q100 -40 °C to +125 °C DHVQFN20 74HCT573BQ-Q100 Description plastic small outline package; 20 leads; body width 7.5 mm Version SOT163-1 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 plastic dual in-line compatible thermal SOT764-1 enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm Nexperia 4. Functional diagram 74HC573-Q100; 74HCT573-Q100 Octal D-type transparent latch; 3-state 2 D0 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 LATCH 1 to 8 3-STATE OUTPUTS Q0 19 Q1 18 Q2 17 Q3 16 Q4 15 Q5 14 Q6 13 Q7 12 Fig. 1. Functional diagram 11 LE 1 OE mna809 D0 D1 D2 D3 D4 D5 D6 D7 DQ DQ DQ DQ DQ DQ DQ DQ LATCH 1 LE LATCH 2 LE LATCH 3 LE LATCH 4 LE LATCH 5 LE LATCH 6 LE LATCH 7 LE LATCH 8 LE LE OE Q0 Q1 Q2 Fig. 2. Logic diagram 1 2 OE D0 Q0 19 3 D1 Q1 18 4 D2 Q2 17 5 D3 Q3 16 6 D4 Q4 15 7 D5 Q5 14 8 D6 Q6 13 9 D7 Q7 12 LE 11 mna.


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