Document
74HC594-Q100; 74HCT594-Q100
8-bit shift register with output register
Rev. 2 — 13 June 2016
Product data sheet
1. General description
The 74HC594-Q100; 74HCT594-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).
The 74HC594-Q100; 74HCT594-Q100 is an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct overriding clears (SHR and STR) are provided on both the shift and storage registers. A serial output (Q7S) is provided for cascading purposes.
Both the shift and storage register clocks are positive-edge triggered. If both clocks are connected together, the shift register is always one count pulse ahead of the storage register.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C
Synchronous serial input and output Complies with JEDEC standard No.7A 8-bit parallel output Shift and storage registers have independent direct clear and clocks Independent clocks for shift and storage registers 100 MHz (typical) ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
3. Applications
Serial-to parallel data conversion Remote control holding register
Nexperia
74HC594-Q100; 74HCT594-Q100
8-bit shift register with output register
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74HC594D-Q100 40 C to +125 C
74HCT594D-Q100
74HC594PW-Q100 40 C to +125 C
Name SO16
TSSOP16
5. Functional diagram
Description plastic small outline package; 16 leads; body width 3.9 mm
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
Version SOT109-1
SOT403-1
'6 6+&3
6+5
67&3 675
67$*(6+,)75(*,67(5
46
%,76725$*(5(*,67(5
Fig 1. Functional diagram
4 4 4 4 4 4 4 4
PEF
6+&3 67&3
'6
46 4 4 4 4 4 4 4 4
6+5 675 PEF
Fig 2. Logic symbol
675 67&3
6+5 6+&3
'6
5 &
5 65* &
' ' 4 4 4 4 4 4 4 4 46
PEF
Fig 3. IEC logic symbol
74HC_HCT594_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 13 June 2016
© Nexperia B.V. 2017. All rights reserved
2 of 25
Nexperia
74HC594-Q100; 74HCT594-Q100
8-bit shift register with output register
'6 6+&3
6+5
67&3 675
67$*(
'4 ))6+ &3
5
67$*(672 '4
67$*(
'4 ))6+ &3
5
'4
))67
&3 5
'4
))67
&3 5
46
Fig 4. Logic diagram
6+&3 '6
67&3 6+5 675 4 4 4 4 46
Fig 5. Timing diagram
4 4 4 4 4 4 4
4 PEF PEF
74HC_HCT594_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 13 June 2016
© Nexperia B.V. 2017. All rights reserved
3 of 25
Nexperia
74HC594-Q100; 74HCT594-Q100
8-bit shift register with output register
6. Pinning information
6.1 Pinning
+&4 +&74
4 4 4 4 4 4 4 *1'
9&& 4 '6 675 67&3 6+&3 6+5 46 DDD
Fig 6. Pin configuration SO16
+&4
4 4 4 4 4 4 4 *1'
9&& 4 '6 675 67&3 6+&3 6+5 46
DDD
Fig 7. Pin configuration TSSOP16
6.2 Pin description
Table 2. Pin description Symbol Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 GND Q7S SHR SHCP STCP STR DS VCC
Pin 15, 1, 2, 3, 4, 5, 6, 7 8 9 10 11 12 13 14 16
Description parallel data output ground (0 V) serial data output shift register reset (active LOW) shift register clock input storage register clock input storage register reset (active LOW) serial data input supply voltage
74HC_HCT594_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 13 June 2016
© Nexperia B.V. 2017. All rights reserved
4 of 25
Nexperia
74HC594-Q100; 74HCT594-Q100
8-bit shift register with output register
7. Functional description
Table 3. Function table[1] Function
Clear shift register Clear storage register Load DS into shift register stage 0, advance previous stage data to the next stage Transfer shift register data to storage register and outputs Qn Shift register one count pulse ahead of storage register
Input SHR STR LX XL HX XH HH
SHCP STCP XX XX X X
DS X X H or L X X
[1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH transition; X = don’t care.
8. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
.