Document
74LVC16245A-Q100;
74LVCH16245A-Q100
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
Rev. 3 — 24 September 2021
Product data sheet
1. General description
The 74LVC16245A-Q100; 74LVCH16245A-Q100 is a 16-bit transceiver with 3-state outputs. The device can be used as two 8-bit transceivers or one 16-bit transceiver. The device features two output enables (1OE and 2OE) each controlling eight outputs, and two send/receive (1DIR and 2DIR) inputs for direction control. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
• Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Overvoltage tolerant inputs to 5.5 V • Wide supply voltage range from 1.2 V to 3.6 V • CMOS low power dissipation • MULTIBYTE flow-through standard pin-out architecture • Low inductance multiple power and ground pins for minimum noise and ground bounce • Direct interface with TTL levels • All data inputs have bus hold (74LVCH16245A-Q100 only) • IOFF circuitry provides partial Power-down mode operation • Complies with JEDEC standard:
• JESD8-7A (1.65 V to 1.95 V) • JESD8-5A (2.3 V to 2.7 V) • JESD8-C/JESD36 (2.7 V to 3.6 V) • ESD protection: • MIL-STD-883, method 3015 exceeds 2000V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) • CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V
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3. Ordering information
74LVC16245A-Q100; 74LVCH16245A-Q100
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
Table 1. Ordering information
Type number
Temperature range
74LVC16245ADGG-Q100 74LVCH16245ADGG-Q100 74LVC16245ADGV-Q100 74LVCH16245ADGV-Q100
-40 °C to +125 °C -40 °C to +125 °C
Package Name TSSOP48
TVSOP48
Description
Version
plastic thin shrink small outline package; SOT362-1 48 leads; body width 6.1 mm
plastic thin shrink small outline package; 48 leads; body width 4.4 mm; lead pitch 0.4 mm
SOT480-1
4. Functional diagram
1DIR 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7
Fig. 1. Logic symbol
2DIR
1OE 2A0
1B0 2A1
1B1 2A2
1B2 2A3
1B3 2A4
1B4 2A5
1B5 2A6
1B6 2A7
1B7
2OE 2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 001aaa789
74LVC_LVCH16245A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 24 September 2021
© Nexperia B.V. 2021. All rights reserved
2 / 14
Nexperia
Fig. 2. IEC logic symbol Fig. 3. Bus hold circuit
74LVC16245A-Q100; 74LVCH16245A-Q100
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
1OE 1DIR
2OE 2DIR
G3 3EN1[BA] 3EN2[AB] G6 6EN4[BA] 6EN5[AB]
1A0
1
1B0
2
1A1
1B1
1A2
1B2
1A3
1B3
1A4
1B4
1A5
1B5
1A6
1B6
1A7
1B7
2A0
4
2B0
5
2A1
2B1
2A2
2B2
2A3
2B3
2A4
2B4
2A5
2B5
2A6
2B6
2A7
2B7
001aaa790
VCC data input
to internal circuit mna705
74LVC_LVCH16245A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 24 September 2021
© Nexperia B.V. 2021. All rights reserved
3 / 14
Nexperia
5. Pinning information
74LVC16245A-Q100; 74LVCH16245A-Q100
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
5.1. Pinning
74LVC16245A-Q100 74LVCH16245A-Q100
1DIR 1 1B0 2 1B1 3 GND 4 1B2 5 1B3 6 VCC 7 1B4 8 1B5 9 GND 10 1B6 11 1B7 12 2B0 13 2B1 14 GND 15 2B2 16 2B3 17 VCC 18 2B4 19 2B5 20 GND 21 2B6 22 2B7 23 2DIR 24
48 1OE 47 1A0 46 1A1 45 GND 44 1A2 43 1A3 42 VCC 41 1A4 40 1A5 39 GND 38 1A6 37 1A7 36 2A0 35 2A1 34 GND 33 2A2 32 2A3 31 VCC 30 2A4 29 2A5 28 GND 27 2A6 26 2A7 25 2OE
aaa-005103
Fig. 4. Pin configuration SOT362-1 (TSSOP48) and SOT480-1 (TVSOP48)
5.2. Pin description
Table 2. Pin description Symbol 1DIR, 2DIR 1B0 to 1B7 2B0 to 2B7 GND VCC 1OE, 2OE 1A0 to 1A7 2A0 to 2A7
Pin 1, 24 2, 3, 5, 6, 8, 9, 11, 12 13, 14, 16, 17, 19, 20, 22, 23 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42 48, 25 47, 46, 44, 43, 41, 40, 38, 37 36, 35, 33, 32, 30, 29, 27, 26
Description direction control input data input/output data input/output ground (0 V) supply voltage output enable input (active LOW) data input/output data input/output
74LVC_LVCH16245A_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 24 September 2021
© Nexperia B.V. 2021. All rights reserved
4 / 14
Nexperia
6. .