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74LVCH1T45-Q100 Dataheets PDF



Part Number 74LVCH1T45-Q100
Manufacturers nexperia
Logo nexperia
Description Dual supply translating transceiver
Datasheet 74LVCH1T45-Q100 Datasheet74LVCH1T45-Q100 Datasheet (PDF)

74LVC1T45-Q100; 74LVCH1T45-Q100 Dual supply translating transceiver; 3-state Rev. 5 — 10 February 2022 Product data sheet 1. General description The 74LVC1T45-Q100; 74LVCH1T45-Q100 are single bit, dual supply transceivers with 3-state outputs that enable bidirectional level translation. They feature two 1-bit input-output ports (A and B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied with any voltage between 1.2 V and 5.5 V. T.

  74LVCH1T45-Q100   74LVCH1T45-Q100



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74LVC1T45-Q100; 74LVCH1T45-Q100 Dual supply translating transceiver; 3-state Rev. 5 — 10 February 2022 Product data sheet 1. General description The 74LVC1T45-Q100; 74LVCH1T45-Q100 are single bit, dual supply transceivers with 3-state outputs that enable bidirectional level translation. They feature two 1-bit input-output ports (A and B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied with any voltage between 1.2 V and 5.5 V. This flexibility makes the device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A. The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state. Active bus hold circuitry in the 74LVCH1T45-Q100 holds unused or floating data inputs at a valid logic level. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C • Wide supply voltage range: • VCC(A): 1.2 V to 5.5 V • VCC(B): 1.2 V to 5.5 V • High noise immunity • Maximum data rates: • 420 Mbps (3.3 V to 5.0 V translation) • 210 Mbps (translate to 3.3 V)) • 140 Mbps (translate to 2.5 V) • 75 Mbps (translate to 1.8 V) • 60 Mbps (translate to 1.5 V) • Suspend mode • Latch-up performance exceeds 100 mA per JESD 78 Class II • ±24 mA output drive (VCC = 3.0 V) • Inputs accept voltages up to 5.5 V • Low power consumption: 16 μA maximum ICC • IOFF circuitry provides partial Power-down mode operation • Complies with JEDEC standards: • JESD8-7 (1.2 V to 1.95 V) • JESD8-5 (1.8 V to 2.7 V) • JESD8C (2.7 V to 3.6 V) • JESD36 (4.5 V to 5.5 V) • ESD protection: • HBM JESD22-A114F Class 3A exceeds 4000 V • CDM JESD22-C101E exceeds 1000 V Nexperia 74LVC1T45-Q100; 74LVCH1T45-Q100 Dual supply translating transceiver; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74LVC1T45GW-Q100 -40 °C to +125 °C 74LVCH1T45GW-Q100 74LVC1T45GM-Q100 -40 °C to +125 °C Name TSSOP6 XSON6 Description Version plastic thin shrink small outline package; 6 leads; SOT363-2 body width 1.25 mm plastic extremely thin small outline package; SOT886 no leads; 6 terminals; body 1 × 1.45 × 0.5 mm 4. Marking Table 2. Marking Type number 74LVC1T45GW-Q100 74LVCH1T45GW-Q100 74LVC1T45GM-Q100 Marking code[1] V5 X5 V5 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram DIR 5 A3 VCC(A) Fig. 1. Logic symbol VCC(B) 4B 001aag885 DIR A VCC(A) Fig. 2. Logic diagram B VCC(B) 001aag886 74LVC_LVCH1T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 10 February 2022 © Nexperia B.V. 2022. All rights reserved 2 / 28 Nexperia 74LVC1T45-Q100; 74LVCH1T45-Q100 Dual supply translating transceiver; 3-state 6. Pinning information 6.1. Pinning 74LVC1T45-Q100 74LVCH1T45-Q100 VCC(A) 1 GND 2 6 VCC(B) 5 DIR A3 4B aaa-006758 Fig. 3. Pin configuration SOT363-2 (TSSOP6) 74LVC1T45-Q100 VCC(A) 1 6 VCC(B) GND 2 5 DIR A3 4B aaa-029747 Transparent top view Fig. 4. Pin configuration SOT886 (XSON6) 6.2. Pin description Table 3. Pin description Symbol Pin VCC(A) 1 GND 2 A 3 B 4 DIR 5 VCC(B) 6 Description supply voltage port A and DIR ground (0 V) data input or output data input or output direction control supply voltage port B 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. Supply voltage Input Input/output [1] VCC(A), VCC(B) DIR 1.2 V to 5.5 V L A A=B B input 1.2 V to 5.5 V H input B=A GND [2] X Z Z [1] The input circuit of the data I/O is always active. [2] When either VCC(A) or VCC(B) is at GND level, the device goes into suspend mode. 74LVC_LVCH1T45_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 10 February 2022 © Nexperia B.V. 2022. All rights reserved 3 / 28 Nexperia 74LVC1T45-Q100; 74LVCH1T45-Q100 Dual supply translating transceiver; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions .


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