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74LVC1G10-Q100 Dataheets PDF



Part Number 74LVC1G10-Q100
Manufacturers nexperia
Logo nexperia
Description Single 3-input NAND gate
Datasheet 74LVC1G10-Q100 Datasheet74LVC1G10-Q100 Datasheet (PDF)

74LVC1G10-Q100 Single 3-input NAND gate Rev. 4 — 2 February 2022 Product data sheet 1. General description The 74LVC1G10-Q100 provides a low-power, low-voltage single 3-input NAND gate. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall time. This device is fully specified for partial power-down applications using.

  74LVC1G10-Q100   74LVC1G10-Q100



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74LVC1G10-Q100 Single 3-input NAND gate Rev. 4 — 2 February 2022 Product data sheet 1. General description The 74LVC1G10-Q100 provides a low-power, low-voltage single 3-input NAND gate. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C • Wide supply voltage range from 1.65 V to 5.5 V • High noise immunity • ±24 mA output drive (VCC = 3.0 V) • CMOS low power dissipation • Latch-up performance exceeds 250 mA • Direct interface with TTL levels • Inputs accept voltages up to 5 V • IOFF circuitry provides partial Power-down mode operation • Complies with JEDEC standard: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8C (2.7 V to 3.6 V) • JESD36 (4.5 V to 5.5 V) • ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LVC1G10GW-Q100 -40 °C to +125 °C TSSOP6 Description plastic thin shrink small outline package; 6 leads; body width 1.25 mm Version SOT363-2 Nexperia 74LVC1G10-Q100 Single 3-input NAND gate 4. Marking Table 2. Marking Type number 74LVC1G10GW-Q100 Marking code [1] YM [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram A1 B3 C6 4Y 001aag686 Fig. 1. Logic symbol 1& 3 4 6 001aag687 Fig. 2. IEC logic symbol A B Y C 001aag688 Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74LVC1G10 A1 6C GND 2 5 VCC B3 Fig. 4. Pin configuration SOT363-2 (TSSOP6) 4Y 001aag689 6.2. Pin description Table 3. Pin description Symbol Pin A 1 GND 2 B 3 Y 4 VCC 5 C 6 Description data input ground (0 V) data input data output supply voltage data input 74LVC1G10_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 2 February 2022 © Nexperia B.V. 2022. All rights reserved 2 / 10 Nexperia 74LVC1G10-Q100 Single 3-input NAND gate 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care. Input A B C H H H L X X X L X X X L Output Y L H H H 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO output voltage IO ICC IGND Ptot Tstg output current supply current ground current total power dissipation storage temperature VI < 0 V VO > VCC or VO < 0 V Active mode Power-down mode; VCC = 0 V VO = 0 V to VCC Tamb = -40 °C to +125 °C -0.5 -50 [1] -0.5 - [1] -0.5 [1] -0.5 - - -100 [2] - -65 +6.5 V - mA +6.5 V ±50 mA VCC + 0.5 V +6.5 V ±50 mA 100 mA - mA 250 mW +150 °C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SOT363-2 (TSSOP6) package: Ptot derates linearly with 3.7 mW/K above 83 °C. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage Active mode Power-down mode; VCC = 0 V Tamb ambient temperature Δt/ΔV input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V Min Typ Max Unit 1.65 - 5.5 V 0 - 5.5 V 0 - VCC V 0 - 5.5 V -40 - +125 °C - - 20 ns/V - - 10 ns/V 74LVC1G10_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 2 February 2022 © Nexperia B.V. 2022. All rights reserved 3 / 10 Nexperia 74LVC1G10-Q100 Single 3-input NAND gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions -40 °C to +85 °C Min Typ [1] Max VIH HIGH-level input`voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 0.65VCC - - 1.7 - - VCC = 2.7 V to 3.6 V 2.0 - - VCC = 4.5 V to 5.5 V 0.7VCC - - VIL LOW-level input VCC = 1.65 .


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