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74LVC1G80-Q100 Dataheets PDF



Part Number 74LVC1G80-Q100
Manufacturers nexperia
Logo nexperia
Description Single D-type flip-flop
Datasheet 74LVC1G80-Q100 Datasheet74LVC1G80-Q100 Datasheet (PDF)

74LVC1G80-Q100 Single D-type flip-flop; positive-edge trigger Rev. 3 — 31 January 2022 Product data sheet 1. General description The 74LVC1G80-Q100 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as transl.

  74LVC1G80-Q100   74LVC1G80-Q100



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74LVC1G80-Q100 Single D-type flip-flop; positive-edge trigger Rev. 3 — 31 January 2022 Product data sheet 1. General description The 74LVC1G80-Q100 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and -40 °C to +125 °C • Wide supply voltage range from 1.65 V to 5.5 V • Overvoltage tolerant inputs to 5.5 V • High noise immunity • ±24 mA output drive (VCC = 3.0 V) • CMOS low power dissipation • Direct interface with TTL levels • IOFF circuitry provides partial Power-down mode operation • Latch-up performance exceeds 250 mA • Complies with JEDEC standard: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8C (2.7 V to 3.6 V) • JESD36 (4.5 V to 5.5 V) • ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74LVC1G80GW-Q100 -40 °C to +125 °C 74LVC1G80GV-Q100 -40 °C to +125 °C Name TSSOP5 SC-74A Description plastic thin shrink small outline package; 5 leads; body width 1.25 mm plastic surface-mounted package; 5 leads Version SOT353-1 SOT753 Nexperia 74LVC1G80-Q100 Single D-type flip-flop; positive-edge trigger 4. Marking Table 2. Marking codes Type number 74LVC1G80GW-Q100 74LVC1G80GV-Q100 Marking[1] VT V80 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1D Q4 2 CP Fig. 1. Logic symbol mna649 CP D Fig. 3. Logic diagram C C C TG C C TG C 6. Pinning information 1D 4 2 CP 001aac523 Fig. 2. IEC logic symbol C TG C C TG C Q mna651 6.1. Pinning 74LVC1G80 D1 CP 2 5 VCC GND 3 4Q 001aab662 Fig. 4. Pin configuration SOT353-1 (TSSOP5) and SOT753 (SC-74A) 74LVC1G80_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 January 2022 © Nexperia B.V. 2022. All rights reserved 2 / 14 Nexperia 74LVC1G80-Q100 Single D-type flip-flop; positive-edge trigger 6.2. Pin description Table 3. Pin description Symbol Pin D 1 CP 2 GND 3 Q 4 VCC 5 Description data input clock pulse input ground (0 V) data output supply voltage 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH CP transition; X = don’t care; q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition. Input Output CP D Q ↑ L H ↑ H L L X q 74LVC1G80_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 31 January 2022 © Nexperia B.V. 2022. All rights reserved 3 / 14 Nexperia 74LVC1G80-Q100 Single D-type flip-flop; positive-edge trigger 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC IIK VI IOK VO IO ICC IGND Ptot Tstg supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current total power dissipation storage temperature VI < 0 V VO > VCC or VO < 0 V Active mode Power-down mode; VCC = 0 V VO = 0 V to VCC Tamb = -40 °C to +125 °C -0.5 -50 [1] -0.5 - [1] -0.5 [1] -0.5 - - -100 [2] - -65 +6.5 V - mA +6.5 V ±50 mA VCC + 0.5 V +6.5 V ±50 mA 100 mA - mA 250 mW +150 °C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SOT353-1 (TSSOP5) package: Ptot derates linearly with 3.3 mW/K above 74 °C. For SOT753 (SC-74A) package: Ptot derates linearly with 3.8 mW/K above 85 °C. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage Active mode Power-down mode; VCC = 0 V Tamb ambi.


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