S71KL512SC0

SUPPLEMENT S71KS512SC0 S71KL256SC0 S71KL512SC0 HyperFlash™ and HyperRAM™ Multi-Chip Package 1.8V/3V HyperFlash™ and HyperRAM™ Multi-Chip Package 3 V Distinctive Characteristics ■ HyperFlash™ and HyperRAM™ in Multi-Chip Package (MCP) ❐ 1.8V, 512 Mb HyperFlash and 64 Mbit HyperRAM (S71KS512SC0) ❐ 3.0V, 512 Mb HyperFlash and 64 Mbit HyperRAM (S71KL512SC0) ❐ 3.0V, 256 Mb HyperFlash and 64 Mbit HyperRAM (S71KL256SC0) ❐ FBGA 24-ball, 6  8  1.0 mm package ■ HyperBus Interface ❐ 1.8V I/O, 12 bus signals Differential clock (CK/CK#) ❐ 3.0V I/O, 11 bus signals Single ended clock (CK) ❐ Chip Select (CS#) ❐ 8-bit data bus (DQ[7:0]) ❐ Read-Write Data Strobe (RWDS) Bidirectional Data Strobe/Mask Output at the start of all transactions to indicate refresh latency Output during read transactions as Read Data Strobe Input during write transactions as Write Data Mask (HyperRAM only) ■ Optional Signals ❐ Reset ❐ INT# output to generate external interrupt Busy to Ready Transition ❐ RSTO# Output to generate system level Power-On Reset (POR) User configurable RSTO# Low period ■ High Performance ❐ Double-Data Rate (DDR) Two data transfers per clock ❐ Up to 166-MHz clock rate (333 MB/s) at 1.8V VCC ❐ Up to 100-MHz clock rate (200 MB/s) at 3.0V VCC Cypress Semiconductor Corporation 198 Champion Court Document Number: 002-03902 Rev. *D San Jose, CA 95134-1709 408-943-2600 Revised February 23, 2017 SUPPLEMENT S71KS512SC0 S71KL256SC0 S71KL512SC0 Contents General Descrip...