QUADRUPLE 2-INPUT POSITIVE-NOR GATES
54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES
• Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin...
Description
54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configuration
Minimizes High-Speed Switching Noise
EPIC™ (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity
at 125°C
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These devices contain four independent 2-input NOR gates. They perform the Boolean functions Y = A S B or Y = A + B in positive logic.
The 54AC11002 is characterized for operation over the full military temperature range of – 55°C to 125°C. The 74AC11002 is characterized for operation from – 40°C to 85°C.
FUNCTION TABLE (each gate)
INPUTS AB
OUTPUT Y
HX
L
XH
L
LL
H
SCAS024A – JUNE 1987 – REVISED APRIL 1993
54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE
(TOP VIEW)
1A 1Y 2Y GND GND 3Y 4Y 4B
1 2 3 4 5 6 7 8
16 1B 15 2A 14 2B 13 VCC 12 VCC 11 3A 10 3B
9 4A
54AC11002 . . . FK PACKAGE (TOP VIEW)
2B VCC NC VCC 3A
2A
3 2 1 20 19 4 18
3B
1B 5
17 4A
NC 6
16 NC
1A 7
15 4B
1Y 8
14 4Y
9 10 11 12 13
2Y GND
NC GND
3Y
NC – No internal connection
logic symbol†
1 1A
16 1B
15 2A
14 2B
11 3A
10 3B
9 4A
8 4B
≥1
2 1Y
3 2Y
6 3Y
7 4Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram (positive logic)
1A 1 1B 16
2A 15 2B 14
3A 11 3B 10
4A ...
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