74AC11244

D EPIC™ (Enhanced-Performance Implanted CMOS ) 1-µm Process D 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers D Flow-Through Architecture Optimizes PCB Layout D Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise D 500-mA Typical Latch-Up Immunity at 125°C D Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic DIPs (NT) 74AC11244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998 DB, DW, NT, OR PW PACKAGE (TOP VIEW) 1Y1 1Y2 1Y3 1Y4 GND GND GND GND 2Y1 2Y2 2Y3 2Y4 1 2 3 4 5 6 7 8 9 10 11 12 24 1OE 23 1A1 22 1A2 21 1A3 20 1A4 19 VCC 18 VCC 17 2A1 16 2A2 15 2A3 14 2A4 13 2OE description The 74AC11244 is an octal buffer or line driver designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as two 4-bit buffers or one 8-bit buffer, with active-low output-enable (OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The 74AC11244 is characterized for operation from...