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54AC11112 Dataheets PDF



Part Number 54AC11112
Manufacturers Texas Instruments
Logo Texas Instruments
Description DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
Datasheet 54AC11112 Datasheet54AC11112 Datasheet (PDF)

54AC11112, 74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS073A – JUNE 1989 – REVISED APRIL 1993 • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise • EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm Process • 500-mA Typical Latch-Up Immunity at 125°C • ESD Protection Exceeds 2000 V, MIL STD-883C Method 3015 • Package Options Include Plastic Small- Outline Packages, Ceramic Chip Carriers, a.

  54AC11112   54AC11112


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54AC11112, 74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS073A – JUNE 1989 – REVISED APRIL 1993 • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise • EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm Process • 500-mA Typical Latch-Up Immunity at 125°C • ESD Protection Exceeds 2000 V, MIL STD-883C Method 3015 • Package Options Include Plastic Small- Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs 54AC11112 . . . J PACKAGE 74AC11112 . . . D OR N PACKAGE (TOP VIEW) 1PRE 1Q 1Q GND 2Q 2Q 2PRE 2J 1 2 3 4 5 6 7 8 16 1J 15 1K 14 1CLK 13 1CLR 12 VCC 11 2CLR 10 2CLK 9 2K 54AC11112 . . . FK PACKAGE (TOP VIEW) description 1CLK 1CLR NC V CC 2CLR These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. 1K 1J NC 1PRE 1Q 3 2 1 20 19 4 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2CLK 2K NC 2J 2PRE 1Q GND NC 2Q 2Q NC – No internal connection The 54AC11112 is characterized for operation over the full military temperature range of – 55°C to 125°C. The 74AC11112 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE (each gate) INPUTS OUTPUTS PRE CLR CLK J K Q Q LHXXXHL HLXXXLH L L X X X H{ H{ H H ↓ L L QO QO HH ↓ H L H L HH↓ LHLH HH↓HH Toggle H H H X X QO QO † This configuration is nonstable; that is, it will not persist when either PRE or CLR returns to its inactive (high) level. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. •POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright © 1993, Texas Instruments Incorporated 2–1 54AC11112, 74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS073A – JUNE 1989 – REVISED APRIL 1993 logic symbol† 1PRE 1J 1CLK 1K 1CLR 2PRE 2J 2CLK 2K 2CLR 1 16 14 15 13 7 8 10 9 11 S 1J C1 1K R S 2J C2 2K R 2 1Q 3 1Q 6 2Q 5 2Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. logic diagram, each flip-flop (positive logic) PRE J C C K CLK CLR TG C C C C TG C TG C C TG C Q Q absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –ā65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2–2 •POST OFFICE BOX 655303 DALLAS, TEXAS 75265 recommended operating conditions VCC Supply voltage VIH High-level input voltage VIL Low-level input vol.


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