74AC11112

54AC11112, 74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS073A – JUNE 1989 – REVISED APRIL 1993 Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C ESD Protection Exceeds 2000 V, MIL STD-883C Method 3015 Package Options Include Plastic Small- Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs 54AC11112 . . . J PACKAGE 74AC11112 . . . D OR N PACKAGE (TOP VIEW) 1PRE 1Q 1Q GND 2Q 2Q 2PRE 2J 1 2 3 4 5 6 7 8 16 1J 15 1K 14 1CLK 13 1CLR 12 VCC 11 2CLR 10 2CLK 9 2K 54AC11112 . . . FK PACKAGE (TOP VIEW) description 1CLK 1CLR NC V CC 2CLR These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. 1K ...