54AC11175

Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise t EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These positive-edge-triggered flipflops implement D-type flip-flop logic with a direct clear input. Information at the D inputs that meets the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The 54AC11175 is characterized for operation over the full military temperature range of – 55°C to 125°C. The 74AC11175 is characterized for operation from – 40°C to 85°C. GND GND CND GND 3Q 54AC11175, 74AC11175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR SCAS090 – DECEMBER 1989 – REVISED APRIL 1993 54AC11175 . . . J PACKAGE 74AC11175 . . . DW or N PACKAGE (TOP VIEW) 1Q 2Q 2Q GND GND GND GND 3Q 3Q 4Q 1 2 3 4 5 6 7 8 9 10 20 1Q 19 CLR 18 1D 17 2D 16 VCC 15 VCC 14 3D 13 4D 12 CLK 11 4Q 54AC11014 . . . FK PACKAGE (TOP VIEW) 1D 2D VCC VCC 3D CLR 1Q 1Q 2Q 2Q ...