74AC11373

D Eight Latches in a Single Package D 3-State Bus-Driving True Outputs D Full Parallel Access for Loading D Buffered Control Inputs D Flow-Through Architecture Optimizes PCB Layout D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise D EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process D 500-mA Typical Latch-Up Immunity at 125°C D Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (NT) 74AC11373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS213A – MAY 1987 – REVISED APRIL 1996 DB, DW, OR NT PACKAGE (TOP VIEW) 1Q 2Q 3Q 4Q GND GND GND GND 5Q 6Q 7Q 8Q 1 2 3 4 5 6 7 8 9 10 11 12 24 OE 23 1D 22 2D 21 3D 20 4D 19 VCC 18 VCC 17 5D 16 6D 15 7D 14 8D 13 LE description This 8-bit latch features 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the 74AC11373 are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. OE can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The...