74AC11478

Specifically Designed for Data Synchronization Applications 3-State Outputs Drive Bus Lines Directly Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC ™ (Enhanced-Performance Implanted CMOS ) 1-µm Process Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description 74AC11478 OCTAL DUAL-RANK D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS182 – APRIL 1989 – REVISED APRIL 1993 DW OR NT PACKAGE (TOP VIEW) 1Q 2Q 3Q 4Q GND GND GND GND 5Q 6Q 7Q 8Q 1 2 3 4 5 6 7 8 9 10 11 12 24 OE 23 1D 22 2D 21 3D 20 4D 19 VCC 18 VCC 17 5D 16 6D 15 7D 14 8D 13 CLK The 74AC11478 is an 8-bit dual-rank synchronizer circuit designed specifically for data synchronization applications in which the normal setup and hold time specifications are frequently violated. Synchronization of two digital signals operating at different frequencies is a common system problem. This problem is typically solved by synchronizing one of the signals to the local clock through a flip-flop. This solution, however, causes the setup and hold time specifications associated with the flip-flop to be violated. When the setup or hold time of a flip-flop is violated, the output response is uncertain. A flip-flop is metastable if its output hangs up in the region between VIL and VIH. The metastable condition lasts until the flip-flop recovers into one of its two stable states. With conventional flip-flops...