74AC11623

Local Bus-Latch Capability Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages, and Standard Plastic 300-mil DIPs description 74AC11623 OCTAL BUS TRANSCEIVER WITH 3–STATE OUTPUTS SCAS058A – JULY 1987 – REVISED APRIL 1993 DW OR NT PACKAGE (TOP VIEW) A1 A2 A3 A4 GND GND GND GND A5 A6 A7 A8 1 2 3 4 5 6 7 8 9 10 11 12 24 OEAB 23 B1 22 B2 21 B3 20 B4 19 VCC 18 VCC 17 B5 16 B6 15 B7 14 B8 13 OEBA These octal bus transceivers are designed for asynchronous communication between data buses. The control function implementation allows for maximum flexibility in timing. These devices transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the output-enable (OEAB or OEBA) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated. The dual-enable configuration gives these devices the capability to store data by simultaneous enabling of OEAB and OEBA. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (16 in all) will remain at their last states. The 8-bit codes appearing on the two sets of buses wil...