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74AC11652 Dataheets PDF



Part Number 74AC11652
Manufacturers Texas Instruments
Logo Texas Instruments
Description OCTAL BUS TRANSCEIVER AND REGISTER
Datasheet 74AC11652 Datasheet74AC11652 Datasheet (PDF)

74AC11652 OCTAL BUS TRANSCEIVER AND REGISTERS WITH 3-STATE OUTPUTS SCAS088A - DECEMBER 1989 - REVISED APRIL 1996 D Independent Registers and Enables for A and B Buses DW PACKAGE (TOP VIEW) D Multiplexed Real-Time and Stored Data D Inverting Data Paths D Flow-Through Architecture Optimizes PCB Layout D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise OEAB A1 A2 A3 A4 GND 1 2 3 4 5 6 28 CLKAB 27 SAB 26 B1 25 B2 24 B3 23 B4 D EPIC ™ (Enhanced-Performance Implanted CM.

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74AC11652 OCTAL BUS TRANSCEIVER AND REGISTERS WITH 3-STATE OUTPUTS SCAS088A - DECEMBER 1989 - REVISED APRIL 1996 D Independent Registers and Enables for A and B Buses DW PACKAGE (TOP VIEW) D Multiplexed Real-Time and Stored Data D Inverting Data Paths D Flow-Through Architecture Optimizes PCB Layout D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise OEAB A1 A2 A3 A4 GND 1 2 3 4 5 6 28 CLKAB 27 SAB 26 B1 25 B2 24 B3 23 B4 D EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm Process D 500-mA Typical Latch-Up Immunity at 125°C GND GND GND A5 A6 7 8 9 10 11 22 VCC 21 VCC 20 B5 19 B6 18 B7 description A7 12 A8 13 17 B8 16 CLKBA The 74AC11652 consists of bus transceiver OEBA 14 15 SBA circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 74AC11652. Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set remains at its last state. The 74AC11652 is characterized for operation from – 40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1996, Texas Instruments Incorporated •POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1 74AC11652 OCTAL BUS TRANSCEIVER AND REGISTERS WITH 3-STATE OUTPUTS SCAS088A - DECEMBER 1989 - REVISED APRIL 1996 BUS A BUS B BUS A BUS B 1 14 28 16 27 OEAB OEBA CLKAB CLKBA SAB LL XXX REAL-TIME TRANSFER BUS B TO BUS A 15 SBA L 1 14 OEAB OEBA HH 28 CLKAB X 16 CLKBA X 27 SAB L REAL-TIME TRANSFER BUS A TO BUS B 15 SBA X BUS A BUS B BUS A BUS B 1 OEAB X L L 14 28 16 27 OEBA CLKAB CLKBA SAB H ↑XX X X↑X H ↑↑X STORAGE FROM A, B, OR A AND B 15 SBA X X X 1 14 OEAB OEBA HL 28 CLKAB L 16 CLKBA L 27 SAB H 15 SBA H TRANSFER STORED DATA TO A AND/OR B Figure 1. Bus-Management Functions •2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 74AC11652 OCTAL BUS TRANSCEIVER AND REGISTERS WITH 3-STATE OUTPUTS SCAS088A - DECEMBER 1989 - REVISED APRIL 1996 OEAB OEBA INPUTS CLKAB CLKBA SAB FUNCTION TABLE DATA I/O† SBA A1 THRU A8 B1 THRU B8 OPERATION OR FUNCTION LH L L XX Input Input Isolation LH XH HH LX LL ↑ ↑ ↑ L ↑ ↑ XX Input Input L XX Input Unspecified‡ ↑ X‡ X Input Output ↑ X X Unspecified‡ Input ↑ X X‡ Output Input Store A and B data Store A, hold B Store A in both registers Hold A, store B Store B in both registers LL X X XL Output Input Real-time B data to A bus LL X L XH Output Input Stored B data to A bus HH X X LX Input Output Real-time A data to B bus HH L X HX Input Output Stored A data to B bus HL L L HH Output Output Stored A data to B bus and stored B data to A bus † The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs. ‡ Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered to load both registers. logic symbol§ OEBA OEAB CLKBA SBA CLKAB SAB 14 1 16 15 28 27 EN1 [BA] EN2 [AB] C4 G5 C6 G7 2 A1 3 A2 4 A3 5 A4 10 A5 11 A6 12 A7 13 A8 ≥1 1 6D 7 17 5 4D 51 ≥1 2 26 B1 25 B2 24 B3 23 B4 20 B5 19 B6 18 B7 17 B8 § This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. •POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3 74AC11652 OCTAL BUS TRANSCEIVER AND REGISTERS WITH 3-STATE OUTPUTS SCAS088A - DECEMBER 1989 - REVISED APRIL 1996 logic diagram (positive logic) 14 OEBA OEAB 1 CLKBA 16 SBA 15 CLKAB 28 SAB 27 One of Eight Channels A1 2 1D C1 .


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