74ACT11010

ą Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These devices contain three independent 3-input NAND gates. They perform the Boolean functions Y = ASBSC or Y = A + B + C in positive logic. The 54ACT11010 is characterized for operation over the full military temperature range of − 55°C to 125°C. The 74ACT11010 is characterized for operation from − 40°C to 85°C. FUNCTION TABLE (each gate) INPUTS ABC OUTPUT Y HHH L LXX H XLX H XXL H logic symbol† 1 1A 16 1B 15 1C 14 2A 11 2B 10 2C 9 3A 8 3B 7 3C & 2 1Y 3 2Y 6 3Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 54ACT11010, 74ACT11010 TRIPLE 3ĆINPUT POSITIVEĆNAND GATES ą SCAS018A − D2957, JULY 1987 − REVISED APRIL 1993 54ACT11010 . . . J PACKAGE 74ACT11010 . . . D OR N PACKAGE (TOP VIEW) 1A 1Y...