54ACT11021

Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small- Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These devices contain two independent 4-input AND gates. They perform the Boolean functions Y = ASBSCSD or Y = A + B + C + D in positive logic. The 54ACT11021 is characterized for operation over the full military temperature range of – 55°C to 125°C. The 74ACT11021 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE (each gate) INPUTS OUTPUT ABCD Y HHHH H LXXX L XLXX L XXLX L XXXL L logic symbol† 1A 2 1B 1 1C 13 1D 12 2A 10 2B 9 2C 7 2D 6 & 3 1Y 5 2Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. 54ACT11021, 74ACT11021 DUAL 4-INPUT POSITIVE-AND GATES SCAS012B – D2957, JULY 1987 – REVISED APRIL 1993 54ACT11021 . . . J PACKAGE 74ACT11021 . . . D OR N PACKAGE (TOP VIEW) 1B 1A 1Y GND 2Y 2D 2C 1 2 3 4 5 6 7 14 NC 13 1C 12 1D 11 VCC 10 2A 9 2B 8 NC 54ACT11021 . . . FK PACKAGE (TOP VIEW) 1C 1D NC VCC 2A NC 3 2 1 20 19 4 18 2B NC 5 17 NC 1B 6 16 NC NC 7 15 NC 1A 8 14 2C 9 10 11 12 13 1Y GND NC 2Y 2D NC – No internal connection logic diagram (p...