74ACT11280

Inputs Are TTL-Voltage Compatible Generates Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bits Parity Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise t EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These universal, monolithic, 9-bit parity generators/checkers feature odd and even outputs to facilitate operation of either an odd or even parity application. The word-length capability is easily expanded by cascading. The 54ACT11280 is characterized for operation over the full military temperature range of – 55°C to 125°C. The 74ACT11280 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE NUMBER OF INPUTS A THRU I THAT ARE HIGH OUTPUTS S EVEN S ODD 0, 2, 4, 6, 8 HL 1, 3, 5, 7, 9 LH 54ACT11280, 74ACT11280 9-BIT PARITY GENERATORS/CHECKERS SCAS046A – D3148, AUGUST 1988 – REVISED APRIL 1993 54ACT11280 . . . J PACKAGE 74ACT11280 . . . D OR N PACKAGE (TOP VIEW) B A Σ ODD GND Σ EVEN NC I 1 2 3 4 5 6 7 14 C 13 D 12 E 11 VCC 10 F 9G 8H 54ACT11280 . . . FK PACKAGE (TOP VIEW) D E NC V CC F C 3 2 1 20 19 4 18 G NC 5 17 NC B6 16 H NC 7 15 NC A8 14 I 9 10 11 12 13 Σ ODD GND NC Σ EVEN NC NC – No internal connection logic symbol† 2 A 1 B 14 C 13 D 12 E 10 F 9 G ...