74ACT11533

ą Eight Latches in a Single Package 3-State Bus-Driving Inverting Outputs Full Parallel Access for Loading Buffered Control Inputs Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small- Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description 54ACT11533, 74ACT11533 OCTAL DĆTYPE TRANSPARENT LATCHES WITH 3ĆSTATE OUTPUTS SCAS017A − D2957, JULY 1987 − REVISED APRIL 1993 54ACT11533 . . . JT PACKAGE 74ACT11533 . . . DW OR NT PACKAGE (TOP VIEW) 1Q 2Q 3Q 4Q GND GND GND GND 5Q 6Q 7Q 8Q 1 2 3 4 5 6 7 8 9 10 11 12 24 OC 23 1D 22 2D 21 3D 20 4D 19 VCC 18 VCC 17 5D 16 6D 15 7D 14 8D 13 C 54ACT11533 . . . FK PACKAGE (TOP VIEW) 3D 4D VCC NC VCC 5D 6D These eight latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ′ACT11533 are transparent D-type latches. While the enable (C) is high, the Q outputs will follow the complements of the (D) inputs. When the output control OC is taken low, the Q outputs will be latched. The ′ACT11533 is functionally equivalent to the ′ACT11373 ex...