74ACT11543

74ACT11543 OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS136 – D3608, JULY 1990 – REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible 3-State True Outputs Back-to-Back Registers for Storage Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise t EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C description This 8-bit registered transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch enable (LEAB or LEBA) and output enable (GAB or GBA) inputs are provided for each register to permit independent control in either direction of data flow. DW PACKAGE (TOP VIEW) CEBA A1 A2 A3 A4 GND GND GND GND A5 A6 A7 A8 CEAB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 GBA 27 LEBA 26 B1 25 B2 24 B3 23 B4 22 VCC 21 VCC 20 B5 19 B6 18 B7 17 B8 16 LEAB 15 GAB The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data to B. Having CEAB low and LEAB low makes the A-to-B latches transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and GAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B-to-A is similar, but requires the use of CEBA, LEBA, and GBA inputs. The 74ACT11543 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE INPUTS CEAB ...