74ACT11867

74ACT11867 SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR SCAS178 – D3990, DECEMBER 1991 – REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Asynchronous Clear DW PACKAGE (TOP VIEW) Fully Independent Clock Circuit Simplifies Use Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise QA QB QC QD QE GND 1 2 3 4 5 6 28 A 27 B 26 C 25 D 24 E 23 F EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C GND GND GND QF 7 8 9 10 22 VCC 21 VCC 20 G 19 H description The 74ACT11867 is a synchronous presettable QG QH RCO 11 12 13 18 ENP 17 ENT 16 S0 binary counter featuring an internal carry CLK 14 15 S1 look-ahead for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the eight flip-flops on the rising (positive-going) edge of the clock waveform. The counters are fully programmable; that is, the outputs may each be preset to either logic level. The load-mode circuitry allows parallel loading of the cascaded counters. As loading is synchronous, selecting ...