AND REGISTERS. 74ACT16648 Datasheet

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74ACT16648 Datasheet
Recommendation 74ACT16648 Datasheet
Part 74ACT16648
Description 16-BIT TRANSCEIVERS AND REGISTERS
Feature 74ACT16648; 54ACT16648, 74ACT16648 16-BIT TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS188A – MAY 1991 – .
Manufacture etcTI
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Texas Instruments 74ACT16648
54ACT16648, 74ACT16648
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS188A – MAY 1991 – REVISED APRIL 1996
D Members of the Texas Instruments
Widebus Family
D Inputs Are TTL-Voltage Compatible
D Independent Registers for A and B Buses
D Inverting Data Path
D Multiplexed Real-Time and Stored Data
D Flow-Through Architecture Optimizes
PCB Layout
D Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D EPIC(Enhanced-Performance Implanted
CMOS) 1-µm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’ACT16648 are 16-bit bus transceivers that
consist of D-type flip-flops and control circuitry
arranged for multiplexed transmission of data
directly from the data bus or from the internal
storage registers. The devices can be used as two
8-bit transceivers or one 16-bit transceiver. Data
on the A or B bus is clocked into the registers on
the low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the 74ACT16648.
54ACT16648 . . . WD PACKAGE
74ACT16648 . . . DL PACKAGE
(TOP VIEW)
1DIR
1CLKAB
1SAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2SAB
2CLKAB
2DIR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 1OE
55 1CLKBA
54 1SBA
53 GND
52 1B1
51 1B2
50 VCC
49 1B3
48 1B4
47 1B5
46 GND
45 1B6
44 1B7
43 1B8
42 2B1
41 2B2
40 2B3
39 GND
38 2B4
37 2B5
36 2B6
35 VCC
34 2B7
33 2B8
32 GND
31 2SBA
30 2CLKBA
29 2OE
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port can be stored in either register or in both. The
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry
used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition
between stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation
mode (OE high), A data can be stored in one register and/or B data can be stored in the other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
The 74ACT16648 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1996, Texas Instruments Incorporated
1



Texas Instruments 74ACT16648
54ACT16648, 74ACT16648
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS188A – MAY 1991 – REVISED APRIL 1996
description (continued)
The 54ACT16648 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT16648 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE DIR CLKAB CLKBA SAB SBA
DATA I/O
A1–A8
B1–B8
OPERATION OR FUNCTION
XX
X XX
Input
Unspecified†
Store A, B unspecified†
XX
X
X X Unspecified†
Input
Store B, A unspecified†
HX
XX
Input
Input
Store A and B data
HX
L
L
X
X
Input disabled
Input disabled
Isolation, hold storage
LL
X
X XL
Output
Input
Real-time B data to A bus
LL
X
L XH
Output
Input
Stored B data to A bus
LH
X
X LX
Input
Output
Real-time A data to B bus
LH
L
X HX
Input
Output
Stored A data to B bus
The data-output functions may be enabled or disabled by a variety of level combinations at OE and DIR. Data-input functions are always enabled;
i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265



Texas Instruments 74ACT16648
54ACT16648, 74ACT16648
16-BIT TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS188A – MAY 1991 – REVISED APRIL 1996
56 1
2 55 3 54
OE DIR CLKAB CLKBA SAB SBA
LL
XXXL
REAL-TIME TRANSFER
BUS B TO BUS A
56 1 2 55 3 54
OE DIR CLKAB CLKBA SAB SBA
LH
X
XLX
REAL-TIME TRANSFER
BUS A TO BUS B
56 1
2 55 3 54
OE DIR CLKAB CLKBA SAB SBA
XX
X X X
XX XXX
HX
↑↑XX
STORAGE FROM
A, B, OR A AND B
56 1 2 55 3 54
OE DIR CLKAB CLKBA SAB SBA
LLX
L XH
LHL
X HX
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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