MSP50P37 Datasheet | MIXED-SIGNAL PROCESSORS





MSP50P37 PDF File (Datasheet) Download

Part Number MSP50P37
Description MIXED-SIGNAL PROCESSORS
Manufacture etcTI
Total Page 9 Pages
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Features: D Dual Programmable LPC-12 Speech Synthe sizers D Simultaneous LPC and PCM Wavef orms D 8-Bit Microprocessor with 61 ins tructions D 32 Twelve-Bit Words and 224 Bytes of RAM D 3.3V to 6.5V CMOS Techn ology for Low Power Dissipation D Direc t Speaker Drive Capability D Mask Selec table Internal or External Clock D Inte rnal Clock Generator that Requires No E xternal Components D Two Software-Selec table Clock Speeds D 10-kHz or 8-kHz Sp eech Sample Rate MSP50C32, MSP50C33, M SP50C34 MSP50P34, MSP50C37, MSP50P37 MI XED-SIGNAL PROCESSORS SPSS019A – MAY 1997 – REVISED OCTOBER 1998 N PACKAGE (TOP VIEW) PA6 PA5 PA4 PA3 PA2 PA1 PB 1/OSC OUT OSC IN 1 2 3 4 5 6 7 8 16 P A7 15 PB0 14 PA0 13 DAC + 12 DAC – 11 VDD 10 VSS 9 INIT description The MS P50x3x family uses a revolutionary arch itecture to combine an 8-bit microproce ssor, two speech synthesizers, ROM, RAM , and I/O in a low-cost single-chip sys tem. The architecture uses the same ari thmetic logic unit (ALU) for the two synthesizers and the microproces.

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D Dual Programmable LPC-12 Speech
Synthesizers
D Simultaneous LPC and PCM Waveforms
D 8-Bit Microprocessor with 61 instructions
D 32 Twelve-Bit Words and 224 Bytes of RAM
D 3.3V to 6.5V CMOS Technology for Low
Power Dissipation
D Direct Speaker Drive Capability
D Mask Selectable Internal or External Clock
D Internal Clock Generator that Requires No
External Components
D Two Software-Selectable Clock Speeds
D 10-kHz or 8-kHz Speech Sample Rate
MSP50C32, MSP50C33, MSP50C34
MSP50P34, MSP50C37, MSP50P37
MIXED-SIGNAL PROCESSORS
SPSS019A – MAY 1997 – REVISED OCTOBER 1998
N PACKAGE
(TOP VIEW)
PA6
PA5
PA4
PA3
PA2
PA1
PB1/OSC OUT
OSC IN
1
2
3
4
5
6
7
8
16 PA7
15 PB0
14 PA0
13 DAC +
12 DAC –
11 VDD
10 VSS
9 INIT
description
The MSP50x3x family uses a revolutionary architecture to combine an 8-bit microprocessor, two speech
synthesizers, ROM, RAM, and I/O in a low-cost single-chip system. The architecture uses the same arithmetic
logic unit (ALU) for the two synthesizers and the microprocessor, thus reducing chip area and cost and enabling
the microprocessor to do a multiply operation in 0.8 µs. The MSP50x3x family features two independent
channels of linear predictive coding (LPC), which synthesize high-quality speech at a low data rate. Pulse-code
modulation (PCM) can produce music or sound effects. LPC and PCM can be added together to produce a
composite result. For more information, see the MSP50x3x User’s Guide (literature number SPSU006).
Table 1. MSP50x3x Family
DEVICE
MSP50C32
MSP50C33
MSP50C34
MSP50P34
MSP50C37
MSP50P37
AMOUNT OF ROM/PROM
16K bytes mask ROM
32K bytes mask ROM
64K bytes mask ROM
64K bytes PROM
16K bytes mask ROM
16K bytes PROM
FEATURES
9/10 I/O lines
9/10 I/O lines
9/10 I/O lines, 24 I/O lines in die form
9/10 I/O lines
18 I/O lines, A/D converter/analog amplifier
18 I/O lines, A/D converter/analog amplifier
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1998, Texas Instruments Incorporated
3

                    
     






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