SMJ320MCM42C

D Performance: -- 80 Million Floating-Point Operations Per Second (MFLOPS) With 496-MBps-Burst I/O Rate for 40-MHz Modules -- Zero-Wait-State Local Memory for Each Processor D Organization: -- 128K-Word × 32-Bit Static Random-Access Memory (SRAM) (SMJ320MCM42D) -- 256K-Word × 32-Bit SRAM (SMJ320MCM42C) D Compliant With MIL-PRF-38535 QML D Dual C40 Performance With Local Memory Requiring Only 8.7 Square Inches of Board Space D Enhanced Performance Offered By Multichip-Module Solution -- SMJ320MCM42C -- 67% Reduction in Number of Interconnects -- 54% Reduction (Minimum) in Board Area -- Estimated 38% Reduction in Power Dissipation Due to Reduced Parasitic Capacitance and Interconnect Lengths -- SMJ320MCM42D -- 56% Reduction in Number of Interconnects -- 30% Reduction (Minimum) in Board Area -- Estimated 20% Reduction in Power Dissipation Due to Reduced Parasitic Capacitance and Interconnect Lengths D Four Memory Ports for High Data Bandwidth -- Two Full 2G-Word External Buses D Two Internal Buses Mapped to Memory -- 128K-Word × 32-Bit SRAM for Each C40 Local Bus (SMJ320MCM42D) -- 256K-Word × 32-Bit SRAM for Each C40 Local Bus (SMJ320MCM42C) D Ten External Communication Ports for Direct Processor-to-Processor Communication SMJ320MCM42C, SMJ320MCM42D DUAL SMJ320C40 MULTICHIP MODULE SGKS001D -- JULY 1997 -- REVISED OCTOBER 2001 HFN PACKAGE‡ (TOP VIEW) 408 307 1 306 102 205 103 204 ‡ Terminal assignment information is provided by the terminal assignments table. Package is shown fo...