SN54ABT652

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Drive Outputs (− 32-mA IOH, 64-mA IOL ) Package Options Include Plastic Small-Outline ((DW)) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs description SN54ABT652, SN74ABT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3ĆSTATE OUTPUTS SCBS070D − JULY 1991 − REVISED JULY 1994 SN54ABT652 . . . JT PACKAGE SN74ABT652 . . . DB, DW, OR NT PACKAGE (TOP VIEW) CLKAB SAB OEAB A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 VCC 23 CLKBA 22 SBA 21 OEBA 20 B1 19 B2 18 B3 17 B4 16 B5 15 B6 14 B7 13 B8 SN54ABT652 . . . FK PACKAGE (TOP VIEW) OEAB SAB CLKAB NC VCC CLKBA SBA These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the t...