SY100ELT21L Datasheet PDF Download, Microchip





(PDF) SY100ELT21L Datasheet Download

Part Number SY100ELT21L
Description 3.3V Differential LVPECL-to-LVTTL Translator
Manufacture Microchip
Total Page 12 Pages
PDF Download Download SY100ELT21L Datasheet PDF

Features: SY100ELT21L 3.3V Differential LVPECL-to -LVTTL Translator Features • 3.3V Po wer Supply • 2.0 ns Typical Propagati on Delay • Low Power • Differential LVPECL Inputs • 24 mA TTL Outputs Flow-Through Pinouts • Available in 8-Lead SOIC Package General Descripti on The SY100ELT21L is a single differen tial LVPECL-to-LVTTL translator that us es a single +3.3V power supply. Because LVPECL (low voltage positive ECL) leve ls are used, only +3.3V and ground are required. The small outline 8-lead SOIC package and low skew single gate desig n make the ELT21L ideal for application s that require the translation of a clo ck or data signal where minimal space, low power, and low cost are critical. V BB allows a differential, single-ended, or AC-coupled interface to the device. If used, the VBB output should be bypa ssed to VCC with a 0.01 μF capacitor. Under open input conditions, the /D wil l be biased at a VCC/2 voltage level an d the D input will be pulled to ground. This condition will force the Q output.

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SY100ELT21L
3.3V Differential LVPECL-to-LVTTL Translator
Features
• 3.3V Power Supply
• 2.0 ns Typical Propagation Delay
• Low Power
• Differential LVPECL Inputs
• 24 mA TTL Outputs
• Flow-Through Pinouts
• Available in 8-Lead SOIC Package
General Description
The SY100ELT21L is a single differential
LVPECL-to-LVTTL translator that uses a single +3.3V
power supply. Because LVPECL (low voltage positive
ECL) levels are used, only +3.3V and ground are
required. The small outline 8-lead SOIC package and
low skew single gate design make the ELT21L ideal for
applications that require the translation of a clock or
data signal where minimal space, low power, and low
cost are critical.
VBB allows a differential, single-ended, or AC-coupled
interface to the device. If used, the VBB output should
be bypassed to VCC with a 0.01 μF capacitor.
Under open input conditions, the /D will be biased at a
VCC/2 voltage level and the D input will be pulled to
ground. This condition will force the Q output low to
provide added stability.
The ELT21L is compatible with positive ECL 100K logic
levels.
Package Type
SY100ELT21L
8-Lead SOIC
(Top View)
NC 1
D2
PECL
D3
VBB 4
8 VCC
TTL 7 Q
6 NC
5 GND
2019 Microchip Technology Inc.
DS20006213A-page 1

                    
              






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