SY100EP195V

SY100EP195V 3.3V/5V 1.6 GHz Programmable Delay Features Pin-for-Pin, Plug-In Compatible to the ON Semiconductor MC100EP195 Maximum Frequency >1.6 GHz Programmable Range: 2.1 ns to 10.8 ns 10 ps Increments PECL Mode Operating Range: VCC = 3.0V to 5.5V with VEE = 0V NECL Mode Operating Range: VCC = 0V with VEE = –3.0V to –5.5V Open Input Default State Safety Clamp on Inputs A Logic-High on the /EN pin will Force Q to Logic-Low D[0:10] Can Accept Either ECL, CMOS, or TTL Inputs VBB Output Reference Voltage Available in a 32-Pin TQFP Package Applications Clock De-skewing Timing Adjustment Aperture Centering General Description The SY100EP195V is a programmable delay line, varying the time a logic signal takes to traverse from IN to Q. This delay can vary from about 2.1 ns to about 10.8 ns. The input can be PECL, LVPECL, NECL, or LVNECL. The delay varies in discrete steps based on a control word presented to the SY100EP195V. The 10-bit width of this latched control register allows for delay increments of approximately 10 ps. An eleventh control bit allows the cascading of multiple SY100EP195V devices, for a wider delay range. Each additional SY100EP195V effectively doubles the delay range available. For maximum flexibility, the control register interface accepts CMOS or TTL level signals, as well as the input level at the IN, /IN pins. Package Type SY100EP195V 32-Lead TQFP (T) (Top View) 32 31 30 29 28 27 26 25 D8 D9 D10 IN /IN VBB VEF VCF 1 2 3 ...