SY100EP32V Datasheet PDF Download, Microchip





(PDF) SY100EP32V Datasheet Download

Part Number SY100EP32V
Description 5V/3.3V ECL/2 Divider
Manufacture Microchip
Total Page 18 Pages
PDF Download Download SY100EP32V Datasheet PDF

Features: SY100EP32V 5V/3.3V ECL ÷2 Divider Feat ures • Guaranteed Maximum Frequency > 4 GHz • 3.3V and 5V Power Supply Opt ions • Guaranteed Propagation Delay < 440 ps over Temperature • Open Input Default State • Wide Operating Tempe rature Range: –40°C to +85°C • Av ailable in 8-Pin MSOP Package Package T ype SY100EP32V 8-Lead MSOP RESET 1 CLK 2 /CLK 3 VBB 4 8 VCC R 7Q ÷2 6 /Q 5 VEE General Description The SY100EP32V is an integrated ÷2 divider with diff erential clock inputs. The VBB pin, an internally generated voltage supply, is available to this device only. For sin gle-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB m ay also rebias AC-coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V BB should be left open. The RESET pin i s asynchronous and is asserted on the r ising edge. Upon power-up, the internal flip-flops will attain a random state; the .

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SY100EP32V
5V/3.3V ECL ÷2 Divider
Features
• Guaranteed Maximum Frequency > 4 GHz
• 3.3V and 5V Power Supply Options
• Guaranteed Propagation Delay < 440 ps over
Temperature
• Open Input Default State
• Wide Operating Temperature Range: –40°C to
+85°C
• Available in 8-Pin MSOP Package
Package Type
SY100EP32V
8-Lead MSOP
RESET 1
CLK 2
/CLK 3
VBB 4
8 VCC
R
7Q
÷2
6 /Q
5 VEE
General Description
The SY100EP32V is an integrated ÷2 divider with
differential clock inputs.
The VBB pin, an internally generated voltage supply, is
available to this device only. For single-ended input
conditions, the unused differential input is connected to
VBB as a switching reference voltage. VBB may also
rebias AC-coupled inputs. When used, decouple VBB
and VCC via a 0.01 μF capacitor and limit current
sourcing or sinking to 0.5 mA. When not used, VBB
should be left open.
The RESET pin is asynchronous and is asserted on the
rising edge. Upon power-up, the internal flip-flops will
attain a random state; the RESET allows for the
synchronous use of multiple EP32 in a system.
Under open input conditions, the CLK input and the
reset input will be pulled to GND. The /CLK input will be
biased at half of the supply voltage. The 100K series
includes internal temperature compensation circuitry.
2019 Microchip Technology Inc.
DS20006171A-page 1

                    
                    






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