SY100EP33V Datasheet: ECL/4 Divider





SY100EP33V ECL/4 Divider Datasheet

Part Number SY100EP33V
Description ECL/4 Divider
Manufacture Microchip
Total Page 16 Pages
PDF Download Download SY100EP33V Datasheet PDF

Features: SY100EP33V 5V/3.3V, 4 GHz, ECL ÷4 Divid er Features • Guaranteed Maximum Fre quency > 4 GHz • 3.3V and 5V Power Su pply Options • Guaranteed Propagation Delay CLK to Q < 460 ps Over Temperatu re • Open Input Default State • Wid e Operating Temperature Range: –40°C to +85°C • Available in 8-Pin MSOP Package Package Type SY100EP33V 8-Lead MSOP RESET 1 CLK 2 /CLK 3 VBB 4 8 VC C R 7Q ÷2 6 /Q 5 VEE General Descript ion The SY100EP33V is an integrated ÷4 divider with differential clock inputs . The VBB pin, an internally generated voltage supply, is available to this de vice only. For single-ended input condi tions, the unused differential input is connected to VBB as a switching refere nce voltage. VBB may also rebias AC-cou pled inputs. When used, decouple VBB an d VCC via a 0.01 μF capacitor and limi t current sourcing or sinking to 0.5 mA . When not used, VBB should be left ope n. The RESET pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a .

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SY100EP33V
5V/3.3V, 4 GHz, ECL ÷4 Divider
Features
• Guaranteed Maximum Frequency > 4 GHz
• 3.3V and 5V Power Supply Options
• Guaranteed Propagation Delay CLK to Q
< 460 ps Over Temperature
• Open Input Default State
• Wide Operating Temperature Range: –40°C to
+85°C
• Available in 8-Pin MSOP Package
Package Type
SY100EP33V
8-Lead MSOP
RESET 1
CLK 2
/CLK 3
VBB 4
8 VCC
R
7Q
÷2
6 /Q
5 VEE
General Description
The SY100EP33V is an integrated ÷4 divider with
differential clock inputs.
The VBB pin, an internally generated voltage supply, is
available to this device only. For single-ended input
conditions, the unused differential input is connected to
VBB as a switching reference voltage. VBB may also
rebias AC-coupled inputs. When used, decouple VBB
and VCC via a 0.01 μF capacitor and limit current
sourcing or sinking to 0.5 mA. When not used, VBB
should be left open.
The RESET pin is asynchronous and is asserted on the
rising edge. Upon power-up, the internal flip-flops will
attain a random state; the RESET allows for the
synchronous use of multiple EP33 in a system.
Under open input conditions, the CLK input and the
RESET input will be pulled to GND. The /CLK input will
be biased at half of the supply voltage. The 100K series
includes internal temperature compensation circuitry.
2019 Microchip Technology Inc.
DS20006166A-page 1

                    
                    






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