5V/3.3V, 4 GHz, ECL ÷4 Divider
• Guaranteed Maximum Frequency > 4 GHz
• 3.3V and 5V Power Supply Options
• Guaranteed Propagation Delay CLK to Q
< 460 ps Over Temperature
• Open Input Default State
• Wide Operating Temperature Range: –40°C to
• Available in 8-Pin MSOP Package
The SY100EP33V is an integrated ÷4 divider with
differential clock inputs.
The VBB pin, an internally generated voltage supply, is
available to this device only. For single-ended input
conditions, the unused differential input is connected to
VBB as a switching reference voltage. VBB may also
rebias AC-coupled inputs. When used, decouple VBB
and VCC via a 0.01 μF capacitor and limit current
sourcing or sinking to 0.5 mA. When not used, VBB
should be left open.
The RESET pin is asynchronous and is asserted on the
rising edge. Upon power-up, the internal flip-flops will
attain a random state; the RESET allows for the
synchronous use of multiple EP33 in a system.
Under open input conditions, the CLK input and the
RESET input will be pulled to GND. The /CLK input will
be biased at half of the supply voltage. The 100K series
includes internal temperature compensation circuitry.
2019 Microchip Technology Inc.